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Message-Id: <1411643839-64925-2-git-send-email-jaz@semihalf.com>
Date: Thu, 25 Sep 2014 13:17:18 +0200
From: Grzegorz Jaszczyk <jaz@...ihalf.com>
To: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Cc: tglx@...utronix.de, jason@...edaemon.net,
ezequiel.garcia@...e-electrons.com,
gregory.clement@...e-electrons.com,
thomas.petazzoni@...e-electrons.com, alior@...vell.com,
tawfik@...vell.com, mw@...ihalf.com, jaz@...ihalf.com
Subject: [PATCH 1/2] irqchip: armada-370-xp: fix MSI interrupt handling
The MSI interrupts use the 16 high doorbells, which are notified by using IRQ1
of the main interrupt controller.
The MSI interrupts were handled correctly for Armada-XP and Armada-370 but not
for Armada-375 and Armada-38x, which use chained handler for the MPIC.
This commit fixes that by checking proper interrupt number in chained handler
for the MPIC.
Signed-off-by: Grzegorz Jaszczyk <jaz@...ihalf.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@...e-electrons.com>
---
drivers/irqchip/irq-armada-370-xp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 574aba0..91424c4 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -417,9 +417,9 @@ static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
- if (irqmap & BIT(0)) {
+ if (irqmap & BIT(1)) {
armada_370_xp_handle_msi_irq(NULL, true);
- irqmap &= ~BIT(0);
+ irqmap &= ~BIT(1);
}
for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
--
1.8.3.1
--
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