linux-kernel - Re: [PATCH] clk: rockchip: rk3288: add reset indices for SOFTRST9-11

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Message-ID: <CAD=FV=UOHc2xLmSJdJbZTgcvJ7xZXPeGZkGGfCRySeKh6q+nJQ@mail.gmail.com>
Date:	Thu, 25 Sep 2014 08:27:57 -0700
From:	Doug Anderson <dianders@...omium.org>
To:	Mark yao <mark.yao@...k-chips.com>
Cc:	Mike Turquette <mturquette@...aro.org>,
	Heiko Stübner <heiko@...ech.de>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Daniel Kurtz <djkurtz@...omium.org>,
	戴克霖 (Jack) <dkl@...k-chips.com>,
	Eddie Cai <eddie.cai@...k-chips.com>,
	Jianqun Xu <xjq@...k-chips.com>,
	柯飞雄 <kfx@...k-chips.com>,
	Tao Huang <huangtao@...k-chips.com>,
	Chris <zyw@...k-chips.com>,
	闫孝军 <yxj@...k-chips.com>,
	jeff chen <cym@...k-chips.com>,
	Shunqian Zheng <zhengsq@...k-chips.com>,
	晓腾王 <caesar.wang@...k-chips.com>,
	Kever Yang <kever.yang@...k-chips.com>
Subject: Re: [PATCH] clk: rockchip: rk3288: add reset indices for SOFTRST9-11

Mark,

On Fri, Sep 12, 2014 at 4:45 AM, Mark yao <mark.yao@...k-chips.com> wrote:
> The patch add the rest of the indices of the additional reset
> registers from the updated TRM.
>
> Signed-off-by: Mark yao <mark.yao@...k-chips.com>
> ---
>  include/dt-bindings/clock/rk3288-cru.h | 43 ++++++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
>
> diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
> index ebcb460..e65d522 100644
> --- a/include/dt-bindings/clock/rk3288-cru.h
> +++ b/include/dt-bindings/clock/rk3288-cru.h
> @@ -276,3 +276,46 @@
>  #define SRST_USBHOST1_CON      140
>  #define SRST_USB_ADP           141
>  #define SRST_ACC_EFUSE         142
> +
> +#define SRST_CORESIGHT         144
> +#define SRST_PD_CORE_AHB_NOC   145
> +#define SRST_PD_CORE_APB_NOC   146
> +#define SRST_PD_CORE_MP_AXI    147
> +#define SRST_GIC               148
> +#define SRST_LCDC_PWM0         149
> +#define SRST_LCDC_PWM1         150
> +#define SRST_VIO0_H2P_BRG      151
> +#define SRST_VIO1_H2P_BRG      152
> +#define SRST_RGA_H2P_BRG       153
> +#define SRST_HEVC              154
> +#define SRST_TSADC             159
> +
> +#define SRST_DDRPHY0           160
> +#define SRST_DDRPHY0_APB       161
> +#define SRST_DDRCTRL0          162
> +#define SRST_DDRCTRL0_APB      163
> +#define SRST_DDRPHY0_CTRL      164
> +#define SRST_DDRPHY1           165
> +#define SRST_DDRPHY1_APB       166
> +#define SRST_DDRCTRL1          167
> +#define SRST_DDRCTRL1_APB      168
> +#define SRST_DDRPHY1_CTRL      169
> +#define SRST_DDRMSCH0          170
> +#define SRST_DDRMSCH1          171

Interestingly 170 and 171 show as Reserved in my TRM...  ...but if
that's what the reserved bits map to then I have no objection.

> +#define SRST_CRYPTO            174
> +#define SRST_C2C_HOST          175
> +
> +#define SRST_LCDC1_AXI         176
> +#define SRST_LCDC1_AHB         177
> +#define SRST_LCDC1_DCLK                178
> +#define SRST_UART0             179
> +#define SRST_UART1             180
> +#define SRST_UART2             181
> +#define SRST_UART3             182
> +#define SRST_UART4             183
> +#define SRST_SIMC              186
> +#define SRST_PS2C              187
> +#define SRST_TSP               188
> +#define SRST_TSP_CLKIN0                189
> +#define SRST_TSP_CLKIN1                190
> +#define SRST_TSP_27M           191

Reviewed-by: Doug Anderson <dianders@...omium.org>
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