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Date:	Fri, 26 Sep 2014 11:28:38 +0200
From:	Arnd Bergmann <arnd@...db.de>
To:	Russell King - ARM Linux <linux@....linux.org.uk>
Cc:	Daniel Thompson <daniel.thompson@...aro.org>,
	Will Deacon <will.deacon@....com>,
	"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"benh@...nel.crashing.org" <benh@...nel.crashing.org>,
	"chris@...kel.net" <chris@...kel.net>,
	"cmetcalf@...era.com" <cmetcalf@...era.com>,
	"davem@...emloft.net" <davem@...emloft.net>,
	"deller@....de" <deller@....de>,
	"dhowells@...hat.com" <dhowells@...hat.com>,
	"geert@...ux-m68k.org" <geert@...ux-m68k.org>,
	"heiko.carstens@...ibm.com" <heiko.carstens@...ibm.com>,
	"hpa@...or.com" <hpa@...or.com>,
	"jcmvbkbc@...il.com" <jcmvbkbc@...il.com>,
	"jesper.nilsson@...s.com" <jesper.nilsson@...s.com>,
	"mingo@...hat.com" <mingo@...hat.com>,
	"monstr@...str.eu" <monstr@...str.eu>,
	"paulmck@...ux.vnet.ibm.com" <paulmck@...ux.vnet.ibm.com>,
	"rdunlap@...radead.org" <rdunlap@...radead.org>,
	"sam@...nborg.org" <sam@...nborg.org>,
	"schwidefsky@...ibm.com" <schwidefsky@...ibm.com>,
	"starvik@...s.com" <starvik@...s.com>,
	"takata@...ux-m32r.org" <takata@...ux-m32r.org>,
	"tglx@...utronix.de" <tglx@...utronix.de>,
	"tony.luck@...el.com" <tony.luck@...el.com>,
	"broonie@...aro.org" <broonie@...aro.org>,
	"thierry.reding@...il.com" <thierry.reding@...il.com>
Subject: Re: [PATCH v3 00/17] Cross-architecture definitions of relaxed MMIO accessors

On Friday 26 September 2014 09:40:19 Russell King - ARM Linux wrote:
> 
> How would a 32-bit architecture know whether it should read the least
> significant 32-bit or the most significant 32-bit part of the 64-bit
> register first.  What would be right for one driver may not ben correct
> for another.  Hence, this decision should only be made by the driver
> wanting the accessor, and not having the accessor symbol defined should
> be the trigger for the driver to handle the problem themselves.

Some 32-bit architectures can trigger 64-bit bus cycles using well
defined accesses using register pairs. Meta seems to fit into this
category:

static inline u64 __raw_readq(const volatile void __iomem *addr)
{
       u64 ret;
       asm volatile("GETL %0,%t0,[%1]"
                    : "=da" (ret)
                    : "da" (addr)
                    : "memory");
       return ret;
}

Most other architectures I think cannot do this however, and would
turn the access into two separate bus cycles, which in addition to
the problem you mentioned could also result in side-effects from
doing an access at the wrong offset, so we definitely can't rely
on having these functions.

	Arnd
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