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Date:	Mon, 29 Sep 2014 09:12:26 -0400
From:	Christopher Covington <cov@...eaurora.org>
To:	Doug Anderson <dianders@...omium.org>
CC:	olof@...om.net, mark.rutland@....com, devicetree@...r.kernel.org,
	Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
	Daniel Lezcano <daniel.lezcano@...aro.org>, pawel.moll@....com,
	ijc+devicetree@...lion.org.uk, Marc Zyngier <marc.zyngier@....com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Sudeep Holla <Sudeep.Holla@....com>,
	Will Deacon <will.deacon@....com>,
	linux-kernel@...r.kernel.org, galak@...eaurora.org,
	robh+dt@...nel.org, Catalin Marinas <Catalin.Marinas@....com>,
	Nathan Lynch <Nathan_Lynch@...tor.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Sonny Rao <sonnyrao@...omium.org>,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v3] clocksource: arch_timer: Allow the device tree to
 specify the physical timer

Hi Doug,

On 09/11/2014 01:00 PM, Doug Anderson wrote:
> Some 32-bit (ARMv7) systems are architected like this:
> 
> * The firmware doesn't know and doesn't care about hypervisor mode and
>   we don't want to add the complexity of hypervisor there.
> 
> * The firmware isn't involved in SMP bringup or resume.
> 
> * The ARCH timer come up with an uninitialized offset between the
>   virtual and physical counters.  Each core gets a different random
>   offset.
> 
> * The device boots in "Secure SVC" mode.

I believe this can safely be detected by whether a write to CNTFRQ succeeds
(handling the UNDEF on failure). I've tested this approach in what I've
determined to be the 19 valid combinations of the following options.

* AArch64 EL3, AArch32 EL3, no EL3
* AArch64 EL2, AArch32 EL2, no EL2
* Start in SVC_N, SVC_S, HYP_N, MON_S

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.
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