linux-kernel - Re: [PATCH 1/1] x86: Quark: Enable correct cache size/type reporting

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Date:	Mon, 29 Sep 2014 09:40:08 -0400
From:	Dave Jones <davej@...hat.com>
To:	"Bryan O'Donoghue" <pure.logic@...us-software.ie>
Cc:	tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
	x86@...nel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/1] x86: Quark: Enable correct cache size/type reporting

On Mon, Sep 29, 2014 at 03:06:12AM +0100, Bryan O'Donoghue wrote:
 > Quark X1000 lacks cpuid(4). It has cpuid(2) but returns no cache
 > descriptors we can work with i.e. cpuid(2) returns
 > eax=0x00000001 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
 > 
 > Quark X1000 contains a 16k 4-way set associative unified L1 cache
 > with 256 sets
 > 
 > This patch emulates cpuid(4) in a similar way to other x86
 > processors like AMDs which don't support cpuid(4). The Quark code
 > is based on the existing AMD code.
 
This looks like it would work, but I wonder if it would be a lot
simpler to do something like what we do in centaur_size_cache()
which is the other case I recall where we had to override
the CPUs definition of cache size.

	Dave

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