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Message-ID: <A765B125120D1346A63912DDE6D8B6315E3D3F@NTXXIAMBX02.xacn.micron.com>
Date:	Wed, 1 Oct 2014 14:24:41 +0000
From:	Bean Huo 霍斌斌 (beanhuo) 
	<beanhuo@...ron.com>
To:	Marek Vasut <marex@...x.de>
CC:	"dwmw2@...radead.org" <dwmw2@...radead.org>,
	Brian Norris <computersforpeace@...il.com>,
	"shijie8@...il.com" <shijie8@...il.com>,
	"geert+renesas@...der.be" <geert+renesas@...der.be>,
	"grmoore@...era.com" <grmoore@...era.com>,
	"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

>> For Micron spi norflash,enables or disables quad I/O protocol ,which 
>> controled by EVCR(Enhanced Volatile Configuration Register) Quad I/O 
>> protocol bit 7.When EVCR bit 7 is reset to 0, the spi norflash will 
>> operate in quad I/O following the next WRITE ENHANCED VOLATILE 
>> CONFIGURATION command.

>You only do one WRITE ENHANCED VOLATILE CONFIGURATION command in the patch, so this text doesn't add up.

>Try something like this:
>-->8--
>This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.

>For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controled by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7. When EVCR bit 7 is reset to 0, the SPI NOR flash will operate in quad I/O mode.
>--8<--

>What do you think ?
Perfect,I will modify my commit message and sumbit it again.thanks.

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