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Date:	Fri, 3 Oct 2014 16:08:07 +0100
From:	Mark Brown <broonie@...nel.org>
To:	Dmitry Lavnikevich <d.lavnikevich@...-solutions.com>
Cc:	shawn.guo@...escale.com, kernel@...gutronix.de, robh+dt@...nel.org,
	pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	linux@....linux.org.uk, lgirdwood@...il.com, perex@...ex.cz,
	tiwai@...e.de, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
	alsa-devel@...a-project.org
Subject: Re: [PATCH v4 4/4] ASoC: tlv320aic3x: fix PLL D configuration

On Fri, Oct 03, 2014 at 04:18:56PM +0300, Dmitry Lavnikevich wrote:
> Current caching implementation during regcache_sync() call bypasses
> all register writes of values that are already known as default
> (regmap reg_defaults). Same time in TLV320AIC3x codecs register 5

Applied, thanks.  This should really have been sent separately to the
other patches - it's not in any way specific to the board and there's no
dependency in either direction.

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