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Date:	Mon, 06 Oct 2014 11:05:44 -0700
From:	David Daney <ddaney.cavm@...il.com>
To:	Leonid Yegoshin <Leonid.Yegoshin@...tec.com>
CC:	linux-mips@...ux-mips.org, Zubair.Kakakhel@...tec.com,
	david.daney@...ium.com, peterz@...radead.org,
	paul.gortmaker@...driver.com, davidlohr@...com,
	macro@...ux-mips.org, chenhc@...ote.com, zajec5@...il.com,
	james.hogan@...tec.com, keescook@...omium.org,
	alex@...x-smith.me.uk, tglx@...utronix.de, blogic@...nwrt.org,
	jchandra@...adcom.com, paul.burton@...tec.com,
	qais.yousef@...tec.com, linux-kernel@...r.kernel.org,
	ralf@...ux-mips.org, markos.chandras@...tec.com,
	manuel.lauss@...il.com, akpm@...ux-foundation.org,
	lars.persson@...s.com
Subject: Re: [PATCH 2/3] MIPS: Setup an instruction emulation in VDSO protected
 page instead of user stack

On 10/03/2014 08:17 PM, Leonid Yegoshin wrote:
> Historically, during FPU emulation MIPS runs live BD-slot instruction in stack.
> This is needed because it was the only way to correctly handle branch
> exceptions with unknown COP2 instructions in BD-slot. Now there is
> an eXecuteInhibit feature and it is desirable to protect stack from execution
> for security reasons.
> This patch moves FPU emulation from stack area to VDSO-located page which is set
> write-protected for application access. VDSO page itself is now per-thread and
> it's addresses and offsets are stored in thread_info.
> Small stack of emulation blocks is supported because nested traps are possible
> in MIPS32/64 R6 emulation mix with FPU emulation.
>

Can you explain how this per-thread mapping works.

I am especially interested in what happens when a different thread from 
the thread using the special mapping, issues flush_tlb_mm(), and 
invalidates the TLBs on all CPUs.  How does the TLB entry for the 
special mapping survive this?

David Daney

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