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Message-Id: <1412674438-26160-1-git-send-email-kever.yang@rock-chips.com>
Date: Tue, 7 Oct 2014 17:33:56 +0800
From: Kever Yang <kever.yang@...k-chips.com>
To: heiko@...ech.de, Mike Turquette <mturquette@...aro.org>
Cc: dianders@...omium.org, sonnyrao@...omium.org,
addy.ke@...k-chips.com, cf@...k-chips.com, xjq@...k-chips.com,
hj@...k-chips.com, huangtao@...k-chips.com, dkl@...k-chips.com,
Kever Yang <kever.yang@...k-chips.com>,
Russell King <linux@....linux.org.uk>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Kumar Gala <galak@...eaurora.org>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
linux-rockchip@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
linux-arm-kernel@...ts.infradead.org
Subject: [PATCH 0/2] init some clock rate from dts for rk3288
This patch add init rate for PLLs and some bus clock from dts for rk3288,
add two clock rate of 400M and 500M into rate table for we will use it.
Kever Yang (2):
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
ARM: dts: enable init rate for clock
arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++
drivers/clk/rockchip/clk-rk3288.c | 2 ++
2 files changed, 12 insertions(+)
--
1.9.1
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