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Date:	Tue,  7 Oct 2014 17:33:58 +0800
From:	Kever Yang <kever.yang@...k-chips.com>
To:	heiko@...ech.de, Mike Turquette <mturquette@...aro.org>
Cc:	dianders@...omium.org, sonnyrao@...omium.org,
	addy.ke@...k-chips.com, cf@...k-chips.com, xjq@...k-chips.com,
	hj@...k-chips.com, huangtao@...k-chips.com, dkl@...k-chips.com,
	Kever Yang <kever.yang@...k-chips.com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Russell King <linux@....linux.org.uk>,
	linux-arm-kernel@...ts.infradead.org,
	linux-rockchip@...ts.infradead.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH 2/2] ARM: dts: enable init rate for clock

We need to initialize PLL rate and some of bus clock rate while
kernel init, for there is no other module will do that.

Signed-off-by: Kever Yang <kever.yang@...k-chips.com>
---

 arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..2f4519b 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -455,6 +455,16 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+				  <&cru PLL_NPLL>, <&cru ACLK_CPU>,
+				  <&cru HCLK_CPU>, <&cru PCLK_CPU>,
+				  <&cru ACLK_PERI>, <&cru HCLK_PERI>,
+				  <&cru PCLK_PERI>;
+		assigned-clock-rates = <594000000>, <400000000>,
+				       <500000000>, <300000000>,
+				       <150000000>, <75000000>,
+				       <300000000>, <150000000>,
+				       <75000000>;
 	};
 
 	grf: syscon@...70000 {
-- 
1.9.1

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