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Date:	Mon, 6 Oct 2014 17:28:02 -0700
From:	Andrew Pinski <pinskia@...il.com>
To:	Rich Felker <dalias@...c.org>
Cc:	David Daney <ddaney@...iumnetworks.com>,
	Andy Lutomirski <luto@...capital.net>,
	David Daney <ddaney.cavm@...il.com>,
	GNU C Library <libc-alpha@...rceware.org>,
	LKML <linux-kernel@...r.kernel.org>, linux-mips@...ux-mips.org,
	David Daney <david.daney@...ium.com>
Subject: Re: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.

On Mon, Oct 6, 2014 at 5:21 PM, Rich Felker <dalias@...c.org> wrote:
> On Mon, Oct 06, 2014 at 05:11:38PM -0700, Andrew Pinski wrote:
>> On Mon, Oct 6, 2014 at 5:05 PM, Rich Felker <dalias@...c.org> wrote:
>> > On Mon, Oct 06, 2014 at 04:48:52PM -0700, David Daney wrote:
>> >> On 10/06/2014 04:38 PM, Andy Lutomirski wrote:
>> >> >On 10/06/2014 02:58 PM, Rich Felker wrote:
>> >> >>On Mon, Oct 06, 2014 at 02:45:29PM -0700, David Daney wrote:
>> >> [...]
>> >> >>This is a huge ill-designed mess.
>> >> >
>> >> >Amen.
>> >> >
>> >> >Can the kernel not just emulate the instructions directly?
>> >>
>> >> In theory it could, but since there can be implementation defined
>> >> instructions, there is no way to achieve full instruction set
>> >> coverage for all possible machines.
>> >
>> > Is the issue really implementation-defined instructions with delay
>> > slots? If so it sounds like a made-up issue. They're not going to
>> > occur in real binaries. Certainly a compiler is not going to generate
>> > implementation-defined instructions, and if you're writing the asm by
>> > hand, you just don't put floating point instructions in the delay
>> > slot.
>>
>> It is not the instruction with delay slot but rather the instruction
>> in the delay slot itself.
>
> An instruction in the delay slot for the instruction being emulated?
> How would that arise? Are there floating point instructions with delay
> slots?

Yes branches.
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