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Date:	Mon, 6 Oct 2014 17:33:18 -0700
From:	David Daney <ddaney@...iumnetworks.com>
To:	Rich Felker <dalias@...c.org>
CC:	Andy Lutomirski <luto@...capital.net>,
	David Daney <ddaney.cavm@...il.com>,
	<libc-alpha@...rceware.org>, <linux-kernel@...r.kernel.org>,
	<linux-mips@...ux-mips.org>, David Daney <david.daney@...ium.com>
Subject: Re: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.

On 10/06/2014 05:05 PM, Rich Felker wrote:
> On Mon, Oct 06, 2014 at 04:48:52PM -0700, David Daney wrote:
>> On 10/06/2014 04:38 PM, Andy Lutomirski wrote:
>>> On 10/06/2014 02:58 PM, Rich Felker wrote:
>>>> On Mon, Oct 06, 2014 at 02:45:29PM -0700, David Daney wrote:
>> [...]
>>>> This is a huge ill-designed mess.
>>>
>>> Amen.
>>>
>>> Can the kernel not just emulate the instructions directly?
>>
>> In theory it could, but since there can be implementation defined
>> instructions, there is no way to achieve full instruction set
>> coverage for all possible machines.
>
> Is the issue really implementation-defined instructions with delay
> slots?

It is the instructions in the delay slots, not the branch instructions 
themselves that are of interest.  But, for the sake of the arguments, 
this is not a critical point.

> If so it sounds like a made-up issue.

It is not a made up issue.

If you want an architecture that has a well defined instruction set, 
stick with x86, Intel will tell you what is good for you and you will 
take whatever they give you.

If you want an architecture where you can add implementation defined 
instructions to do whatever you want, then you use an architecture like 
MIPS.

> They're not going to
> occur in real binaries. Certainly a compiler is not going to generate
> implementation-defined instructions,

Why not?  It will emit any instructions we care to make it emit.  If we 
want it to emit crypto instructions with patented algorithms, then it 
will do that.  But we would still like to use a generic kernel with 
generic FPU support.

The most straight forward way (and the currently implemented way) of 
doing this is to execute the instructions in question out-of-line (on 
the userspace stack).

The question here is:  What is the best way to get to a non-executable 
stack.

The consensus among MIPS developers is that we should continue using the 
out-of-line execution trick, but do it somewhere other than in stack memory.

One way of doing this is to have the kernel magically generate thread 
local memory regions.

Another option is to have userspace manage the out-of-line execution areas.

As is often the case, each approach has different pluses and minuses.


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