lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:	Tue, 7 Oct 2014 11:46:54 -0500
From:	Rob Herring <robherring2@...il.com>
To:	Mark Rutland <mark.rutland@....com>
Cc:	Sonny Rao <sonnyrao@...omium.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Doug Anderson <dianders@...omium.org>,
	Lorenzo Pieralisi <Lorenzo.Pieralisi@....com>,
	Olof Johansson <olof@...om.net>,
	Thomas Gleixner <tglx@...utronix.de>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Will Deacon <Will.Deacon@....com>,
	Catalin Marinas <Catalin.Marinas@....com>,
	Sudeep Holla <Sudeep.Holla@....com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Marc Zyngier <Marc.Zyngier@....com>,
	Pawel Moll <Pawel.Moll@....com>,
	"ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>,
	"galak@...eaurora.org" <galak@...eaurora.org>,
	Nathan Lynch <Nathan_Lynch@...tor.com>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>
Subject: Re: [PATCH v3] clocksource: arch_timer: Allow the device tree to
 specify uninitialized CNTVOFF

On Tue, Oct 7, 2014 at 5:21 AM, Mark Rutland <mark.rutland@....com> wrote:
> Hi Sonny,
>
> This looks generally fine, but there are a couple of minor changes below
> that I would like to see (removing arm64/armv8 confusion, and describing
> the problem more precisely).
>
> On Tue, Oct 07, 2014 at 07:37:32AM +0100, Sonny Rao wrote:
>> From: Doug Anderson <dianders@...omium.org>
>>
>> Some 32-bit (ARMv7) systems are architected like this:
>>
>> * The firmware doesn't know and doesn't care about hypervisor mode and
>>   we don't want to add the complexity of hypervisor there.
>>
>> * The firmware isn't involved in SMP bringup or resume.
>>
>> * The ARCH timer come up with an uninitialized offset (CNTVOFF)
>>   between the virtual and physical counters.  Each core gets a
>>   different random offset.
>>
>> * The device boots in "Secure SVC" mode.
>>
>> * Nothing has touched the reset value of CNTHCTL.PL1PCEN or
>>   CNTHCTL.PL1PCTEN (both default to 1 at reset)
>>
>> On systems like the above, it doesn't make sense to use the virtual
>> counter.  There's nobody managing the offset and each time a core goes
>> down and comes back up it will get reinitialized to some other random
>> value.
>>
>> This adds an optional property which can inform the kernel of this
>> situation, and firmware is free to remove the property if it is going
>> to initialize the CNTVOFF registers when each CPU comes out of reset.
>>
>> Currently, the best course of action in this case is to use the
>> physical timer, which is why it is important that CNTHCTL hasn't been
>> changed from its reset value and it's a reasonable assumption given
>> that the firmware has never entered HYP mode.
>>
>> Note that it's been said that ARM64 (ARMv8) systems the firmware and
>> kernel really can't be architected as described above.  That means
>> using the physical timer like this really only makes sense for ARMv7
>> systems.
>
> Please drop the mention of arm64 here, and just say ARMv8 (they aren't
> quite the same thing, and this confuses the matter). The differences
> w.r.t. privilege boundaries and reset values are properties of ARMv8,
> and would also apply to a 32-bit kernel.
>
>> Signed-off-by: Doug Anderson <dianders@...omium.org>
>> Signed-off-by: Sonny Rao <sonnyrao@...omium.org>
>> ---
>> Changes in v2:
>> - Add "#ifdef CONFIG_ARM" as per Will Deacon
>>
>> Changes in v3:
>> - change property name to arm,cntvoff-not-fw-configured and specify
>>   that the value of CNTHCTL.PL1PC(T)EN must still be the reset value
>>   of 1 as per Mark Rutland
>> ---
>>  Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++
>>  drivers/clocksource/arm_arch_timer.c                 | 9 +++++++++
>>  2 files changed, 17 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
>> index 37b2caf..67837c9 100644
>> --- a/Documentation/devicetree/bindings/arm/arch_timer.txt
>> +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
>> @@ -22,6 +22,14 @@ to deliver its interrupts via SPIs.
>>  - always-on : a boolean property. If present, the timer is powered through an
>>    always-on power domain, therefore it never loses context.
>>
>> +** Optional properties:
>> +
>> +- arm,cntvoff-not-fw-configured : Firmware does not initialize
>> +  CNTVOFF, which may reset to arbitrary and different values on each
>> +  CPU.  CNTHCTL.PL1PC(T)EN must both be 1, which is the reset value
>> +  specificed by the architecture.   Only supported for ARM (not ARM64).
>
> Could we change this to:
>
> - arm,cpu-registers-not-fw-configured: Firmware does not initialize any
>   of the generic timer CPU registers, which contain their
>   architecturally-defined reset values. Only supported for 32-bit
>   systems which follow the ARMv7 architected reset values.

Bikeshedding a bit, but it seems a bit wordy. Are you hoping people
will get tired of typing it and fix their firmware instead? ;) Perhaps
"arm,reg-need-init" or "arm,broken-fw-cfg". The latter name implies
you don't really want to have that option.

Rob
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists