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Message-Id: <1412734798-11116-3-git-send-email-djkurtz@chromium.org>
Date: Wed, 8 Oct 2014 10:19:56 +0800
From: Daniel Kurtz <djkurtz@...omium.org>
To: unlisted-recipients:; (no To-header on input)
Cc: Grant Grundler <grundler@...omium.org>,
Stéphane Marchesin <marcheu@...omium.org>,
Daniel Kurtz <djkurtz@...omium.org>,
Simon Xue <xxm@...k-chips.com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND...),
linux-kernel@...r.kernel.org (open list)
Subject: [PATCH v2 2/3] dt-bindings: iommu: Add documentation for rockchip iommu
Add binding documentation for Rockchip IOMMU.
Signed-off-by: Daniel Kurtz <djkurtz@...omium.org>
Signed-off-by: Simon Xue <xxm@...k-chips.com>
---
.../devicetree/bindings/iommu/rockchip,iommu.txt | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/rockchip,iommu.txt
diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt
new file mode 100644
index 0000000..810e058a
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt
@@ -0,0 +1,26 @@
+Rockchip IOMMU
+==============
+
+A Rockchip DRM iommu translates io virtual addresses to physical addresses for
+its master device. Each slave device is bound to a single master device, and
+shares its clocks, power domain and irq.
+
+Required properties:
+- compatible : Should be "rockchip,iommu"
+- reg : Address space for the configuration registers
+- interrupts : Interrupt specifier for the IOMMU instance
+- interrupt-names : Interrupt name for the IOMMU instance
+- #iommu-cells : Should be <0>. This indicates the iommu is a
+ "single-master" device, and needs no additional information
+ to associate with its master device. See:
+ Documentation/devicetree/bindings/iommu/iommu.txt
+
+Example:
+
+ vopl_mmu: iommu@...f940300 {
+ compatible = "rockchip,iommu";
+ reg = <0xff940300 0x100>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vopl_mmu";
+ #iommu-cells = <0>;
+ };
--
2.1.0.rc2.206.gedb03e5
--
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