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Message-Id: <1412888588-26755-21-git-send-email-kamal@canonical.com>
Date: Thu, 9 Oct 2014 14:00:45 -0700
From: Kamal Mostafa <kamal@...onical.com>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org,
kernel-team@...ts.ubuntu.com
Cc: Olav Haugan <ohaugan@...eaurora.org>,
Will Deacon <will.deacon@....com>,
Kamal Mostafa <kamal@...onical.com>
Subject: [PATCH 3.13 020/163] iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1
3.13.11.9 -stable review patch. If anyone has any objections, please let me know.
------------------
From: Olav Haugan <ohaugan@...eaurora.org>
commit 1fc870c7efa364862c3bc792cfbdb38afea26742 upstream.
Stage-1 context banks do not have the SMMU_CBn_TCR[SL0] field since it
is only applicable to stage-2 context banks.
This patch ensures that we don't set the reserved TCR bits for stage-1
translations.
Signed-off-by: Olav Haugan <ohaugan@...eaurora.org>
Signed-off-by: Will Deacon <will.deacon@....com>
Signed-off-by: Kamal Mostafa <kamal@...onical.com>
---
drivers/iommu/arm-smmu.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 0d3e4e6..91739bf 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -793,8 +793,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
reg |= TTBCR_EAE |
(TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
(TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
- (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
- (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
+ (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
+
+ if (!stage1)
+ reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
+
writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
/* MAIR0 (stage-1 only) */
--
1.9.1
--
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