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Message-ID: <4723.1413216738@turing-police.cc.vt.edu>
Date: Mon, 13 Oct 2014 12:12:18 -0400
From: Valdis.Kletnieks@...edu
To: Gabriel Fernandez <gabriel.fernandez@...aro.org>
Cc: Gabriel FERNANDEZ <gabriel.fernandez@...com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Srinivas Kandagatla <srinivas.kandagatla@...il.com>,
Maxime Coquelin <maxime.coquelin@...com>,
Patrice Chotard <patrice.chotard@...com>,
Russell King <linux@....linux.org.uk>,
Kishon Vijay Abraham I <kishon@...com>,
Grant Likely <grant.likely@...aro.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"kernel@...inux.com" <kernel@...inux.com>,
Lee Jones <lee.jones@...aro.org>,
Harsh Gupta <harsh.gupta@...com>
Subject: Re: [PATCH v3 6/8] phy: miphy28lp: Add SSC support for PCIE
On Mon, 13 Oct 2014 10:16:06 +0200, Gabriel Fernandez said:
> Concerning multiple writing in MIPHY_PLL_SBR_1, the writing of the
> first 0 it's to be sure there is no previous request.
> Then we take account new setting by writing 0x02.
> And then we make it 0 to make sure there is no other pending requests.
>
> I added comments and macro to be more clear (see the code below).
Thanks, that will be a lot clearer to some poor soul down the road who
has to delve in here (possibly to figure out if a new part can use the
same driver and/or what changes need to be made).
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