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Message-ID: <EACD232272DA4849B060F0828564D13B44955ABE1F@ntcex01.corp.netcomm.com.au>
Date: Tue, 14 Oct 2014 16:50:27 +1100
From: Iwo Mergler <Iwo.Mergler@...commwireless.com>
To: Huang Shijie <shijie8@...il.com>,
Boris Brezillon <boris.brezillon@...e-electrons.com>
CC: Mike Voytovich <mvoytovich@...pal.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
Roy Lee <roylee@...pal.com>,
Brian Norris <computersforpeace@...il.com>,
David Woodhouse <dwmw2@...radead.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: RE: [PATCH v3 0/3] mtd: nand: gpmi: add proper raw access support
>
> No, it doesn't seem to be correct.
> But it's an MLC flash, so you'll most probably need to apply this patch
> to nandbiterrs testsuite:
>
> http://code.bulix.org/f69wuu-87021
>
> This patch is flashing the block between each bitflip insertion to
> avoid multiple write without erasure (which, AFAIK, is not supported
> by MLC flashes).
Hi Huang,
just out of interest, have you tried this on the MLC NAND without the patch?
I'm aware that MLC says you shouldn't write multiple times, but that is
with a view towards specified data endurance. I would only expect a few
additional bit errors during the test.
Did you try the overwrite test?
I'm curious how MLC NAND does when subjected to multiple writes.
Best regards,
Iwo
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