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Message-ID: <20141016100648.GB2255@lahna.fi.intel.com>
Date:	Thu, 16 Oct 2014 13:06:48 +0300
From:	Mika Westerberg <mika.westerberg@...el.com>
To:	Chang Rebecca Swee Fun <rebecca.swee.fun.chang@...el.com>
Cc:	Linus Walleij <linus.walleij@...aro.org>,
	GPIO Subsystem Mailing List <linux-gpio@...r.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Denis Turischev <denis.turischev@...pulab.co.il>
Subject: Re: [PATCHv3 2/3] gpio: sch: Add support for Intel Quark X1000 SoC

On Thu, Oct 16, 2014 at 11:51:14AM +0800, Chang Rebecca Swee Fun wrote:
> Intel Quark X1000 provides a total of 16 GPIOs. The GPIOs are split between
> the legacy I/O bridge and the GPIO controller.
> 
> GPIO-SCH is the GPIO pins on legacy bridge for Intel Quark SoC.
> Intel Quark X1000 has 2 GPIOs powered by the core power well and 6 from
> the suspend power well.
> 
> This piece of work is derived from Dan O'Donovan's initial work for Quark
> X1000 enabling.
> 
> Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@...el.com>

Reviewed-by: Mika Westerberg <mika.westerberg@...ux.intel.com>
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