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Message-ID: <CALCETrUxKqNnJQWQUbR-MSzEPj+cvxYgwBA9k9=1n_JOMAx1Ag@mail.gmail.com>
Date: Thu, 16 Oct 2014 08:30:46 -0700
From: Andy Lutomirski <luto@...capital.net>
To: Borislav Petkov <bp@...en8.de>
Cc: Peter Zijlstra <peterz@...radead.org>,
Valdis Kletnieks <Valdis.Kletnieks@...edu>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Paul Mackerras <paulus@...ba.org>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Ingo Molnar <mingo@...hat.com>,
Kees Cook <keescook@...omium.org>,
Andrea Arcangeli <aarcange@...hat.com>,
Erik Bosman <ebn310@....vu.nl>
Subject: Re: [RFC 2/5] x86: Store a per-cpu shadow copy of CR4
On Oct 16, 2014 4:49 AM, "Borislav Petkov" <bp@...en8.de> wrote:
>
> On Tue, Oct 14, 2014 at 03:57:36PM -0700, Andy Lutomirski wrote:
> > Context switches and TLB flushes can change individual bits of CR4.
> > CR4 reads take several cycles, so store a shadow copy of CR4 in a
> > per-cpu variable.
> >
> > To avoid wasting a cache line, I added the CR4 shadow to
> > cpu_tlbstate, which is already touched during context switches.
>
> So does this even show in any workloads as any improvement?
>
Unlear. Assuming that mov from cr4 is more expensive than a cache
miss (which may or may not be true), then kernel TLB flushes will get
cheaper. The main reason I did this is to make switching TSD and PCE
a little cheaper, which might be worthwhile.
I think this may be a huge win on many workloads when running as an
SVM guest. IIUC SVM doesn't have accelerated guest CR4 access.
> Also, what's the rule with reading the shadow CR4? kvm only? Because
> svm_set_cr4() in svm.c reads the host CR4 too.
Whoops.
>
> Should we make all code access the shadow CR4 maybe...
That was the intent. In v2, I'll probably rename read_cr4 to
__read_cr4 to make it difficult to miss things.
>
> --
> Regards/Gruss,
> Boris.
> --
--
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