linux-kernel - [PATCH 04/19] MIPS: Malta: Stop using GIC REG macros

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Date:	Mon, 20 Oct 2014 12:03:51 -0700
From:	Andrew Bresticker <abrestic@...omium.org>
To:	Ralf Baechle <ralf@...ux-mips.org>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Jason Cooper <jason@...edaemon.net>
Cc:	Andrew Bresticker <abrestic@...omium.org>,
	Paul Burton <paul.burton@...tec.com>,
	Qais Yousef <qais.yousef@...tec.com>,
	John Crispin <blogic@...nwrt.org>, linux-mips@...ux-mips.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH 04/19] MIPS: Malta: Stop using GIC REG macros

Stop using the REG macros from gic.h and instead use proper iomem
accessors.

Signed-off-by: Andrew Bresticker <abrestic@...omium.org>
---
 arch/mips/mti-malta/malta-int.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index bcab0b1..864d482 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -37,7 +37,7 @@
 #include <asm/setup.h>
 #include <asm/rtlx.h>
 
-static unsigned long _msc01_biu_base;
+static void __iomem *_msc01_biu_base;
 
 static DEFINE_RAW_SPINLOCK(mips_irq_lock);
 
@@ -293,10 +293,9 @@ void __init arch_init_irq(void)
 		gic_present = 1;
 	} else {
 		if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
-			_msc01_biu_base = (unsigned long)
-					ioremap_nocache(MSC01_BIU_REG_BASE,
+			_msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
 						MSC01_BIU_ADDRSPACE_SZ);
-			gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
+			gic_present = (readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
 					MSC01_SC_CFG_GICPRES_MSK) >>
 					MSC01_SC_CFG_GICPRES_SHF;
 		}
@@ -336,9 +335,9 @@ void __init arch_init_irq(void)
 			 MIPS_GIC_IRQ_BASE);
 		if (!mips_cm_present()) {
 			/* Enable the GIC */
-			i = REG(_msc01_biu_base, MSC01_SC_CFG);
-			REG(_msc01_biu_base, MSC01_SC_CFG) =
-				(i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
+			i = readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
+			writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
+				 _msc01_biu_base + MSC01_SC_CFG_OFS);
 			pr_debug("GIC Enabled\n");
 		}
 		i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;
-- 
2.1.0.rc2.206.gedb03e5

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