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Date:	Tue, 21 Oct 2014 09:30:46 -0500
From:	Nishanth Menon <nm@...com>
To:	Tony Lindgren <tony@...mide.com>
CC:	<linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<devicetree@...r.kernel.org>, <linux-omap@...r.kernel.org>,
	Nishanth Menon <nm@...com>
Subject: [PATCH 1/3] ARM: dts: dra72-evm: Provide explicit pinmux for TPS PMIC

Even thought sys_nirq1 is hardwired on the SoC for the pin, it is
better to configure the pin to the required mux configuration.

Signed-off-by: Nishanth Menon <nm@...com>
---
 arch/arm/boot/dts/dra72-evm.dts |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 4107428..671e473 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -26,6 +26,12 @@
 			0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
 		>;
 	};
+
+	tps65917_pins_default: tps65917_pins_default {
+		pinctrl-single,pins = <
+			0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
+		>;
+	};
 };
 
 &i2c1 {
@@ -38,6 +44,9 @@
 		compatible = "ti,tps65917";
 		reg = <0x58>;
 
+		pinctrl-names = "default";
+		pinctrl-0 = <&tps65917_pins_default>;
+
 		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
 		interrupt-parent = <&gic>;
 		interrupt-controller;
-- 
1.7.9.5

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