linux-kernel - Re: [PATCH] ARM: supplementing IO accessors with 64 bit capability

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Message-ID: <20141022164454.GI15370@e104818-lin.cambridge.arm.com>
Date:	Wed, 22 Oct 2014 17:44:54 +0100
From:	Catalin Marinas <catalin.marinas@....com>
To:	"mathieu.poirier@...aro.org" <mathieu.poirier@...aro.org>
Cc:	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"stefano.stabellini@...citrix.com" <stefano.stabellini@...citrix.com>,
	"ezequiel.garcia@...e-electrons.com" 
	<ezequiel.garcia@...e-electrons.com>,
	Liviu Dudau <Liviu.Dudau@....com>,
	"thomas.petazzoni@...e-electrons.com" 
	<thomas.petazzoni@...e-electrons.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: supplementing IO accessors with 64 bit capability

On Wed, Oct 22, 2014 at 05:06:23PM +0100, mathieu.poirier@...aro.org wrote:
> +#if __LINUX_ARM_ARCH__ >= 5

My old ARMv5 book does not list LDRD/STRD. It looks like they only come
with ARMv5TE. Are there any processors prior to this supported by the
kernel?

> +static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
> +{
> +	asm volatile("strd %1, %0"
> +		     : "+Qo" (*(volatile u64 __force *)addr)
> +		     : "r" (val));
> +}
> +
> +static inline u64 __raw_readq(const volatile void __iomem *addr)
> +{
> +	u64 val;
> +	asm volatile("ldrd %1, %0"
> +		     : "+Qo" (*(volatile u64 __force *)addr),
> +		       "=r" (val));
> +	return val;
> +}
> +#endif

I'm curious why you need these. Do you have a device that needs a 64-bit
single access or you are trying to read two consecutive registers?

-- 
Catalin
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