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Date:	Thu, 23 Oct 2014 10:53:10 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	Stephane Eranian <eranian@...gle.com>
Cc:	LKML <linux-kernel@...r.kernel.org>,
	"mingo@...e.hu" <mingo@...e.hu>,
	"ak@...ux.intel.com" <ak@...ux.intel.com>,
	Jiri Olsa <jolsa@...hat.com>,
	"Liang, Kan" <kan.liang@...el.com>, Borislav Petkov <bp@...en8.de>,
	Maria Dimakopoulou <maria.n.dimakopoulou@...il.com>
Subject: Re: [PATCH v2 0/12] perf/x86: implement HT leak workaround for
 SNB/IVB/HSW

On Wed, Oct 22, 2014 at 11:04:31PM +0200, Stephane Eranian wrote:
> Here is a simple case:
> Limiting each HT to only 2 counters, can be any, 2 out of 4 possible.
> 
> HT0: you measure a MEM* in ctr2, it is started first, and it keeps running
> HT1: you measure PREC_DIST with PEBS (it requires ctr2)
> 
> HT0 is measuring a corrupting event on ctr2, this prevents ctr2 on HT1
> from being used.
> HT1 is starved, it cannot measure PREC_DIST
> 
> Yes you have a quota of 2 out of 4 counters.
> 
> The quota dynamic or static can help mitigate the starvation. The only
> way to eliminate
> it is to force multiplexing even though you are using fewer counters
> than actually avail.

Ah yes, the very narrowly constrained events. Those suck indeed. And I
imagine rotation might not even help here -- rotation doesn't guarantee
SMT1 will try and schedule before SMT0, in fact there are setups
(staggered tick) where its almost guaranteed not to.

Still I suppose for 'normal' event its a much better state, SMT1 can
always schedule some events.
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