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Message-ID: <CAN1soZz8NYxppaY4cXadqynERZ=6ZRAynDtptGAps+yUJZ0Qsw@mail.gmail.com>
Date: Fri, 24 Oct 2014 19:46:11 +0800
From: Haojian Zhuang <haojian.zhuang@...il.com>
To: Zhou Wang <wangzhou.bry@...il.com>
Cc: David Woodhouse <dwmw2@...radead.org>,
Brian Norris <computersforpeace@...il.com>,
linux-mtd@...ts.infradead.org, Mark Rutland <mark.rutland@....com>,
pawel.moll@....com, ijc+devicetree@...lion.org.uk,
Rob Herring <robh+dt@...nel.org>, galak@...eaurora.org,
caizhiyong@...wei.com, "xuwei (O)" <xuwei5@...ilicon.com>,
wangzhou1@...ilicon.com,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
devicetree@...r.kernel.org
Subject: Re: [PATCH v2 1/2] mtd: hisilicon: add a new NAND controller driver
for hisilicon hip04 Soc
On Thu, Oct 23, 2014 at 10:04 PM, Zhou Wang <wangzhou.bry@...il.com> wrote:
> Signed-off-by: Zhou Wang <wangzhou.bry@...il.com>
> ---
> drivers/mtd/nand/Kconfig | 5 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/hisi504_nand.c | 836 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 842 insertions(+)
> create mode 100644 drivers/mtd/nand/hisi504_nand.c
>
I think that you need to run scripts/checkpatch.pl. There're some
warnings reported on this patch.
> +
> + case NAND_CMD_SEQIN:
> + host->offset = column;
> +
It's better not using waterfall style. Maybe you can write it clearly.
case NAND_CMD_SEQIN:
host->offset = column;
set_addr(mtd, column, page_addr);
break;
> + chip->ecc.mode = of_get_nand_ecc_mode(np);
> + /* read ecc-bits from dts */
> + of_property_read_u32(np, "hisi,nand-ecc-bits", &host->ecc_bits);
Do you need to check the ecc_bits at here? Maybe user inputed the
wrong ecc_bits in DTS.
Best Regards
Haojian
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