linux-kernel - Re: [PATCH] ARM: supplementing IO accessors with 64 bit capability

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Message-ID: <CANLsYkzbnNy0kOjuOCQi4LgXGXTYVMH2nc8CFs1dQsgmpD4TrQ@mail.gmail.com>
Date:	Fri, 24 Oct 2014 11:54:12 -0600
From:	Mathieu Poirier <mathieu.poirier@...aro.org>
To:	Catalin Marinas <catalin.marinas@....com>
Cc:	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"stefano.stabellini@...citrix.com" <stefano.stabellini@...citrix.com>,
	"ezequiel.garcia@...e-electrons.com" 
	<ezequiel.garcia@...e-electrons.com>,
	Liviu Dudau <Liviu.Dudau@....com>,
	"thomas.petazzoni@...e-electrons.com" 
	<thomas.petazzoni@...e-electrons.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: supplementing IO accessors with 64 bit capability

On 24 October 2014 10:16, Catalin Marinas <catalin.marinas@....com> wrote:
> On Fri, Oct 24, 2014 at 04:05:13PM +0100, Mathieu Poirier wrote:
>> On 24 October 2014 03:28, Catalin Marinas <catalin.marinas@....com> wrote:
>> > On Wed, Oct 22, 2014 at 08:10:27PM +0100, Mathieu Poirier wrote:
>> >> On 22 October 2014 18:44, Catalin Marinas <catalin.marinas@....com> wrote:
>> >> > On Wed, Oct 22, 2014 at 05:06:23PM +0100, mathieu.poirier@...aro.org wrote:
>> >> >> +static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
>> >> >> +{
>> >> >> +     asm volatile("strd %1, %0"
>> >> >> +                  : "+Qo" (*(volatile u64 __force *)addr)
>> >> >> +                  : "r" (val));
>> >> >> +}
>> >> >> +
>> >> >> +static inline u64 __raw_readq(const volatile void __iomem *addr)
>> >> >> +{
>> >> >> +     u64 val;
>> >> >> +     asm volatile("ldrd %1, %0"
>> >> >> +                  : "+Qo" (*(volatile u64 __force *)addr),
>> >> >> +                    "=r" (val));
>> >> >> +     return val;
>> >> >> +}
>> >> >> +#endif
>> >> >
>> >> > I'm curious why you need these. Do you have a device that needs a 64-bit
>> >> > single access or you are trying to read two consecutive registers?
>> >>
>> >> The fundamental data size of Coresight STM32 for ARMv7 is
>> >> implementation defined and can be 32 or 64bit.  As such stimulus ports
>> >> can support transaction sizes of up to 64 bit.
>> >
>> > The STM programmer's model spec recommends something else (though I find
>> > the "3.6 Data sizes" chapter a bit confusing):
>> >
>> >   To ensure that code is portable between processor micro-architectures
>> >   and system implementations, ARM recommends that only the native data
>> >   size of the machine is used, and smaller sizes. For the 32-bit ARMv7
>> >   architecture, only 8, 16, and 32-bit transfers are recommended. For an
>> >   ARMv8 processor that supports the AArch64 Execution state, it is
>> >   recommended that the fundamental data size of 64-bits is implemented.
>> >
>> > Which means that you should not use readq/writeq on a 32-bit system.
>>
>> Not quite.  ARM documentation IHI0054B (ARM System Trace Macrocell:
>> Programmers' Model Architecture Specification) stipulate that "For
>> systems with an ARMv7 processor, ARM recommends configuration 1 or
>> configuration 2.", where configuration 2 has a fundamental size of 64
>> bit.
>
> As I said, it's confusing. Anyway, you can go ahead and add the
> readq/writeq for ARMv6 and later, though it won't be guaranteed to have
> a 64-bit access, it depends on the bus.

Agreed.

>
> BTW, do you need to define the non-relaxed accessors as well? That would
> be readq/writeq.

No other master in the system is consuming this data and the channels
return '0' on read.  As such I didn't plan on implementing the
non-relaxed accessors.  Would you like me to do so for completeness?

>
> --
> Catalin
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