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Message-ID: <544EB146.1070708@hp.com>
Date:	Mon, 27 Oct 2014 16:55:34 -0400
From:	Waiman Long <waiman.long@...com>
To:	Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>
CC:	Peter Zijlstra <peterz@...radead.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, linux-arch@...r.kernel.org,
	x86@...nel.org, linux-kernel@...r.kernel.org,
	virtualization@...ts.linux-foundation.org,
	xen-devel@...ts.xenproject.org, kvm@...r.kernel.org,
	Paolo Bonzini <paolo.bonzini@...il.com>,
	Boris Ostrovsky <boris.ostrovsky@...cle.com>,
	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
	Rik van Riel <riel@...hat.com>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Raghavendra K T <raghavendra.kt@...ux.vnet.ibm.com>,
	David Vrabel <david.vrabel@...rix.com>,
	Oleg Nesterov <oleg@...hat.com>,
	Scott J Norton <scott.norton@...com>,
	Douglas Hatch <doug.hatch@...com>
Subject: Re: [PATCH v12 09/11] pvqspinlock, x86: Add para-virtualization support

On 10/27/2014 02:02 PM, Konrad Rzeszutek Wilk wrote:
> On Mon, Oct 27, 2014 at 01:38:20PM -0400, Waiman Long wrote:
>> On 10/24/2014 04:54 AM, Peter Zijlstra wrote:
>>> On Thu, Oct 16, 2014 at 02:10:38PM -0400, Waiman Long wrote:
>>>
>>>> Since enabling paravirt spinlock will disable unlock function inlining,
>>>> a jump label can be added to the unlock function without adding patch
>>>> sites all over the kernel.
>>> But you don't have to. My patches allowed for the inline to remain,
>>> again reducing the overhead of enabling PV spinlocks while running on a
>>> real machine.
>>>
>>> Look at:
>>>
>>>    http://lkml.kernel.org/r/20140615130154.213923590@chello.nl
>>>
>>> In particular this hunk:
>>>
>>> Index: linux-2.6/arch/x86/kernel/paravirt_patch_64.c
>>> ===================================================================
>>> --- linux-2.6.orig/arch/x86/kernel/paravirt_patch_64.c
>>> +++ linux-2.6/arch/x86/kernel/paravirt_patch_64.c
>>> @@ -22,6 +22,10 @@ DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs")
>>>   DEF_NATIVE(, mov32, "mov %edi, %eax");
>>>   DEF_NATIVE(, mov64, "mov %rdi, %rax");
>>>
>>> +#if defined(CONFIG_PARAVIRT_SPINLOCKS)&&   defined(CONFIG_QUEUE_SPINLOCK)
>>> +DEF_NATIVE(pv_lock_ops, queue_unlock, "movb $0, (%rdi)");
>>> +#endif
>>> +
>>>   unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len)
>>>   {
>>>          return paravirt_patch_insns(insnbuf, len,
>>> @@ -61,6 +65,9 @@ unsigned native_patch(u8 type, u16 clobb
>>>                  PATCH_SITE(pv_cpu_ops, clts);
>>>                  PATCH_SITE(pv_mmu_ops, flush_tlb_single);
>>>                  PATCH_SITE(pv_cpu_ops, wbinvd);
>>> +#if defined(CONFIG_PARAVIRT_SPINLOCKS)&&   defined(CONFIG_QUEUE_SPINLOCK)
>>> +               PATCH_SITE(pv_lock_ops, queue_unlock);
>>> +#endif
>>>
>>>          patch_site:
>>>                  ret = paravirt_patch_insns(ibuf, len, start, end);
>>>
>>>
>>> That makes sure to overwrite the callee-saved call to the
>>> pv_lock_ops::queue_unlock with the immediate asm "movb $0, (%rdi)".
>>>
>>>
>>> Therefore you can retain the inlined unlock with hardly (there might be
>>> some NOP padding) any overhead at all. On PV it reverts to a callee
>>> saved function call.
>> My concern is that spin_unlock() can be called in many places, including
>> loadable kernel modules. Can the paravirt_patch_ident_32() function able to
>> patch all of them in reasonable time? How about a kernel module loaded later
>> at run time?
> It has too. When the modules are loaded the .paravirt symbols are exposed
> and the module loader patches that.
>
> And during bootup time (before modules are loaded) it also patches everything
> - when it only runs on one CPU.
>> So I think we may still need to disable unlock function inlining even if we
>> used your way kernel site patching.
> No need. Inline should (And is) working just fine.
>> Regards,
>> Longman

Thanks for letting me know about the paravirt patching capability 
available in the kernel. In this case, I would say we should use Peter's 
way of doing unlock without disabling unlock function inlining. That 
will further reduce the performance difference of kernels with and 
without PV.

Cheer,
Longman
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