linux-kernel - Re: [PATCHv2 0/4] Add Altera peripheral memories to EDAC framework

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Message-ID: <544EBA84.7080109@opensource.altera.com>
Date:	Mon, 27 Oct 2014 16:35:00 -0500
From:	Thor Thayer <tthayer@...nsource.altera.com>
To:	Borislav Petkov <bp@...en8.de>
CC:	<dougthompson@...ssion.com>, <m.chehab@...sung.com>,
	<robh+dt@...nel.org>, <pawel.moll@....com>, <mark.rutland@....com>,
	<ijc+devicetree@...lion.org.uk>, <galak@...eaurora.org>,
	<linux@....linux.org.uk>, <dinguyen@...nsource.altera.com>,
	<devicetree@...r.kernel.org>, <linux-doc@...r.kernel.org>,
	<linux-edac@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>, <tthayer.linux@...il.com>,
	<tthayer@...era.com>
Subject: Re: [PATCHv2 0/4] Add Altera peripheral memories to EDAC framework

On 10/27/2014 03:43 PM, Borislav Petkov wrote:
> On Mon, Oct 27, 2014 at 01:50:24PM -0500, Thor Thayer wrote:
>> Do you have any comments about this driver?
> Just a question: why do you have three .c files for something which
> does only error injection and nothing else AFAICT? Why isn't this part
> of altera_edac.c?
>
There are 2 files for doing the error injection (altera_l2_edac.c and 
altera_ocram_edac.c) and then 1 file for the irq handling and probe 
(altera_edac_mgr.c).

The L2 cache and the On-Chip RAM drivers were based on the Calxeda L2 
cache driver and when written as 2 separate files, the resulting code 
was very similar from the probe and error handling standpoint so the 
common code was combined (altera_edac_mgr.c).

The Memory Controller model was used for the SDRAM EDAC (altera_edac.c) 
since it matches the DIMM model.  The MC model didn't seem to fit the 
discrete memories like OCRAM and L2 cache (these files) so I used the 
EDAC device model which agreed with the Calxeda L2 cache driver.

Should I move the EDAC Device probe and error handling from 
altera_edac_mgr.c to altera_edac.c? Can I mix the MC and Device models 
in the same file?

Thanks for reviewing and for commenting.

Thor
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