linux-kernel - Re: [PATCH RESEND 02/12] mmc: sdhci-pxav3: Respect MMC

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Message-ID: <CAPDyKFqOf7JgYv23hqwf-fee5h+588qxPR7=-7ae61XLd+YYKA@mail.gmail.com>
Date:	Mon, 27 Oct 2014 14:38:49 +0100
From:	Ulf Hansson <ulf.hansson@...aro.org>
To:	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
Cc:	Chris Ball <chris@...ntf.net>,
	Antoine Ténart <antoine.tenart@...e-electrons.com>,
	linux-mmc <linux-mmc@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH RESEND 02/12] mmc: sdhci-pxav3: Respect MMC_DDR52 timing
 on uhs signaling

On 21 October 2014 11:22, Sebastian Hesselbarth
<sebastian.hesselbarth@...il.com> wrote:
> commit bb8175a8aa42d731a840cd474e348ac3367eb5a0
>   ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC")
> added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS.
>
> While the differentation may be useful, pxav3 SDHCI controller lacks
> a corresponding check in its custom .set_uhs_signaling callback for
> MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52
> to MMC_TIMING_UHS_DDR50 case.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>

Thanks! Applied for next!

Kind regards
Uffe


> ---
> Cc: Chris Ball <chris@...ntf.net>
> Cc: Ulf Hansson <ulf.hansson@...aro.org>
> Cc: "Antoine Ténart" <antoine.tenart@...e-electrons.com>
> Cc: linux-mmc@...r.kernel.org
> Cc: devicetree@...r.kernel.org
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
> ---
>  drivers/mmc/host/sdhci-pxav3.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 5036d7d39529..b55c807982fe 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -211,6 +211,7 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
>         case MMC_TIMING_UHS_SDR104:
>                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
>                 break;
> +       case MMC_TIMING_MMC_DDR52:
>         case MMC_TIMING_UHS_DDR50:
>                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
>                 break;
> --
> 2.1.1
>
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