linux-kernel - Re: [PATCH v6 4/7] ARM: rockchip: add suspend and resume for RK3288

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Message-ID: <CAD=FV=Vabh6xJOYxkuGiG_AFr2qm26iqL87LJ_CBzK1w+dC9XA@mail.gmail.com>
Date:	Wed, 29 Oct 2014 12:26:32 -0700
From:	Doug Anderson <dianders@...omium.org>
To:	Kevin Hilman <khilman@...nel.org>
Cc:	Chris Zhong <zyw@...k-chips.com>,
	Heiko Stübner <heiko@...ech.de>,
	Mike Turquette <mturquette@...aro.org>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Russell King <linux@....linux.org.uk>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Linus Walleij <linus.walleij@...aro.org>,
	"open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
	Tony Xie <xxx@...k-chips.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6 4/7] ARM: rockchip: add suspend and resume for RK3288

Kevin,

On Wed, Oct 29, 2014 at 12:01 PM, Kevin Hilman <khilman@...nel.org> wrote:
>> +     /* set bit 8 so that system will resume to FAST_BOOT_ADDR */
>> +     regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
>> +                  BIT(SGRF_FAST_BOOT_EN) | BIT(SGRF_FAST_BOOT_EN + 16));
>
> Comment says "bit 8", but code says bit 8 and bit 24, and if bit 24 is
> needed, it should probably get its own #define in the header.

This is Rockchip's "write enable" feature hitting us again.  The upper
16-bits are "write enables" for the lower 16-bits.  So to set bit 8
you set bit 8 to whatever value you want and then 'write enable' by
setting (1 << 8 << 16).  It allows you to avoid read-modify-write.
See this in Rockchip's clk.h:

#define HIWORD_UPDATE(val, mask, shift) \
                ((val) << (shift) | (mask) << ((shift) + 16))
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