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Message-ID: <2482894.SCbMWLltbW@wuerfel>
Date: Thu, 30 Oct 2014 10:03:16 +0100
From: Arnd Bergmann <arnd@...db.de>
To: Kevin Cernekee <cernekee@...il.com>
Cc: f.fainelli@...il.com, tglx@...utronix.de, jason@...edaemon.net,
ralf@...ux-mips.org, lethal@...ux-sh.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
mbizon@...ebox.fr, jogo@...nwrt.org, linux-mips@...ux-mips.org
Subject: Re: [PATCH V2 15/15] irqchip: bcm7120-l2: Enable big endian register accesses on BE kernels
On Wednesday 29 October 2014 19:18:08 Kevin Cernekee wrote:
>
> + flags = IRQ_GC_INIT_MASK_CACHE;
> + if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
> + flags |= IRQ_GC_BE_IO;
> +
>
As I said before, I think you should take this from a DT property instead
of making it dependent on the CPU endianess. Otherwise things go horribly
wrong e.g. when someone runs a big-endian kernel on one of the ARM
based chips.
Arnd
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