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Message-ID: <alpine.DEB.2.11.1410312126430.5308@nanos>
Date: Fri, 31 Oct 2014 21:28:59 +0100 (CET)
From: Thomas Gleixner <tglx@...utronix.de>
To: Borislav Petkov <bp@...en8.de>
cc: Juergen Gross <jgross@...e.com>, hpa@...or.com, x86@...nel.org,
mingo@...hat.com, stefan.bader@...onical.com,
linux-kernel@...r.kernel.org, xen-devel@...ts.xensource.com,
konrad.wilk@...cle.com, ville.syrjala@...ux.intel.com,
david.vrabel@...rix.com, jbeulich@...e.com, toshi.kani@...com,
plagnioj@...osoft.com, tomi.valkeinen@...com, bhelgaas@...gle.com
Subject: Re: [PATCH 01/17] x86: Make page cache mode a real type
On Fri, 31 Oct 2014, Borislav Petkov wrote:
> On Fri, Oct 31, 2014 at 03:00:17PM +0100, Juergen Gross wrote:
> > At the moment there are a lot of places that handle setting or getting
> > the page cache mode by treating the pgprot bits equal to the cache mode.
> > This is only true because there are a lot of assumptions about the setup
> > of the PAT MSR. Otherwise the cache type needs to get translated into
> > pgprot bits and vice versa.
> >
> > This patch tries to prepare for that by introducing a separate type
> > for the cache mode and adding functions to translate between those and
> > pgprot values.
> >
> > To avoid too much performance penalty the translation between cache mode
> > and pgprot values is done via tables which contain the relevant
> > information. Write-back cache mode is hard-wired to be 0, all other
> > modes are configurable via those tables. For large pages there are
> > translation functions as the PAT bit is located at different positions
> > in the ptes of 4k and large pages.
> >
> > Signed-off-by: Stefan Bader <stefan.bader@...onical.com>
> > Signed-off-by: Juergen Gross <jgross@...e.com>
>
> Just a clarification question: how is one to understand this attribution
> here? Is Stefan the original author, was he a reviewer, or? Because this
> SOB chain is misleading...
Bah, wanted to ask that as well. Then got lost in the review and
forgot....
Thanks,
tglx
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