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Date:	Mon, 3 Nov 2014 17:24:55 -0600
From:	Timur Tabi <timur@...eaurora.org>
To:	Mika Westerberg <mika.westerberg@...ux.intel.com>
Cc:	Linus Walleij <linus.walleij@...aro.org>,
	Alexandre Courbot <gnurou@...il.com>,
	Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
	Mathias Nyman <mathias.nyman@...ux.intel.com>,
	"Rafael J. Wysocki" <rjw@...ysocki.net>,
	Ning Li <ning.li@...el.com>, Alan Cox <alan@...ux.intel.com>,
	lkml <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 0/2] pinctrl: Intel Cherryview/Braswell support

On Mon, Nov 3, 2014 at 5:01 AM, Mika Westerberg
<mika.westerberg@...ux.intel.com> wrote:
> Hi,
>
> This is second version of the patch series adding pinctrl/GPIO support
> for Intel Braswell and Cherrryview. The previous version can be found here:
>
> https://lkml.org/lkml/2014/10/27/118
>
> I've dropped patches [2/4] and [3/4] as they are already applied to the
> pinctrl tree.

Mika,

I am also trying to add ACPI enablement to my pinctrl driver (not yet
submitted), but I'm new to ACPI and pin control drivers, so I have a
lot of catching up to do.

In reviewing this patchset, it appears to me that pinctrl-cherryview.c
is a normal pinctrl driver that has an acpi_match_table entry, and
nothing more.

Assuming that this driver is booting on an ACPI system, what is the
mechanism that calls into the driver to configure the pins?  Is there
a definition for pin control in ASL that provides similar
functionality as the pinctrl nodes in a device tree?
--
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