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Message-ID: <5459062F.6090603@amd.com>
Date:	Tue, 4 Nov 2014 11:00:31 -0600
From:	Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
To:	Jiang Liu <jiang.liu@...ux.intel.com>, <marc.zyngier@....com>,
	<mark.rutland@....com>, <jason@...edaemon.net>,
	<tglx@...utronix.de>
CC:	<Catalin.Marinas@....com>, <Will.Deacon@....com>,
	<liviu.dudau@....com>, <Harish.Kasiviswanathan@....com>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-doc@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m
 MSI(-X)

On 11/4/14 07:01, Jiang Liu wrote:
> Hi Suravee,
> 	You may build a two level hierarchy irqdomains. Use the
> utilities in this thread
> http://www.spinics.net/lists/arm-kernel/msg374722.html to build an MSI
> irqdomain to manage MSI controllers
> in PCI devices. And build another irqdomain to manage SPI allocation
> in GICv2.
> 	That is: MSI irqdomain (program MSI registers)  -->
> GIV irqdomain (manage SPIs in GICv2 controller)

That's great. I'll look at this patch in and make use of it to create to 
MSI domain.

Thanks,

Suravee

> Regards!
> Gerry
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