linux-kernel - [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella

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Message-Id: <1415294531-8942-1-git-send-email-afaerber@suse.de>
Date:	Thu,  6 Nov 2014 18:22:10 +0100
From:	Andreas Färber <afaerber@...e.de>
To:	Michal Simek <michal.simek@...inx.com>
Cc:	Olof Johansson <olof@...om.net>,
	Sören Brinkmann <soren.brinkmann@...inx.com>,
	linux-arm-kernel@...ts.infradead.org,
	Andreas Olofsson <andreas@...pteva.com>,
	Matteo Vit <matteo.vit@...rwaredesign.com>,
	Sean Rickerd <srickerd@...e.com>,
	Andreas Färber <afaerber@...e.de>,
	<stable@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Russell King <linux@....linux.org.uk>,
	devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND...),
	linux-kernel@...r.kernel.org (open list)
Subject: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella

The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.

Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.

Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.

Cc: <stable@...r.kernel.org> # 3.17.x
Signed-off-by: Andreas Färber <afaerber@...e.de>
---
 Michal/Olof, please consider this trivial patch as a fix for 3.18.

 arch/arm/boot/dts/zynq-parallella.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index e1f51ca127fe..0429bbd89fba 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,6 +34,10 @@
 	};
 };
 
+&clkc {
+	fclk-enable = <0xf>;
+};
+
 &gem0 {
 	status = "okay";
 	phy-mode = "rgmii-id";
-- 
2.1.2

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