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Message-ID: <20141107041742.GH3698@titan.lakedaemon.net>
Date: Thu, 6 Nov 2014 23:17:42 -0500
From: Jason Cooper <jason@...edaemon.net>
To: Andrew Bresticker <abrestic@...omium.org>
Cc: Ralf Baechle <ralf@...ux-mips.org>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Thomas Gleixner <tglx@...utronix.de>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
John Crispin <blogic@...nwrt.org>,
David Daney <ddaney.cavm@...il.com>,
Qais Yousef <qais.yousef@...tec.com>,
James Hogan <james.hogan@...tec.com>,
Arnd Bergmann <arnd@...db.de>, linux-mips@...ux-mips.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V4 3/4] irqchip: mips-gic: Add device-tree support
Andrew,
On Wed, Oct 29, 2014 at 04:19:49PM -0700, Andrew Bresticker wrote:
> Add device-tree support for the MIPS GIC. Update the GIC irqdomain's
> xlate() callback to handle the three-cell specifier described in the
> MIPS GIC binding document.
>
> Signed-off-by: Andrew Bresticker <abrestic@...omium.org>
> Acked-by: Arnd Bergmann <arnd@...db.de>
> ---
> Changes from v3:
> - use reserved-cpu-vectors property
> - read GIC base from CM if no reg property present
> Changes from v2:
> - rebased on GIC irqchip cleanups
> - updated for change in bindings
> - only parse first CPU vector
> - allow platforms to use EIC mode
> Changes from v1:
> - updated for change in bindings
> - set base address and enable bit in GCR_GIC_BASE
> ---
> drivers/irqchip/irq-mips-gic.c | 92 +++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 87 insertions(+), 5 deletions(-)
I assume this is going though the mips tree...
Acked-by: Jason Cooper <jason@...edaemon.net>
thx,
Jason.
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