linux-kernel - Re: [PATCH 3/5] mfd: ti_am335x_tscadc: Remove unwanted reg_se

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Message-ID: <20141110092645.GE21424@x1>
Date:	Mon, 10 Nov 2014 09:26:45 +0000
From:	Lee Jones <lee.jones@...aro.org>
To:	Vignesh R <vigneshr@...com>
Cc:	Rob Herring <robh+dt@...nel.org>, Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Benoit Cousson <bcousson@...libre.com>,
	Tony Lindgren <tony@...mide.com>,
	Russell King <linux@....linux.org.uk>,
	Jonathan Cameron <jic23@...nel.org>,
	Hartmut Knaack <knaack.h@....de>,
	Dmitry Torokhov <dmitry.torokhov@...il.com>,
	Sebastian Andrzej Siewior <bigeasy@...utronix.de>,
	Lars-Peter Clausen <lars@...afoo.de>,
	Peter Meerwald <pmeerw@...erw.net>,
	Samuel Ortiz <sameo@...ux.intel.com>,
	Felipe Balbi <balbi@...com>, Brad Griffis <bgriffis@...com>,
	Sanjeev Sharma <sanjeev_sharma@...tor.com>,
	Paul Gortmaker <paul.gortmaker@...driver.com>,
	Jan Kardell <jan.kardell@...liq.com>,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-omap@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-iio@...r.kernel.org, linux-input@...r.kernel.org
Subject: Re: [PATCH 3/5] mfd: ti_am335x_tscadc: Remove unwanted reg_se_cache
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On Mon, 10 Nov 2014, Lee Jones wrote:

> On Fri, 07 Nov 2014, Vignesh R wrote:
> 
> > In one shot mode, sequencer automatically disables all enabled steps at
> > the end of each cycle. (both ADC steps and TSC steps) Hence these steps
> > need not be saved in reg_se_cache for clearing these steps at a later
> > stage.
> > Also, when ADC wakes up Sequencer should not be busy executing any of the
> > config steps except for the charge step. Previously charge step was 1 ADC
> > clock cycle and hence it was ignored.
> > 
> > Signed-off-by: Vignesh R <vigneshr@...com>
> > ---
> >  drivers/mfd/ti_am335x_tscadc.c       | 7 +++++--
> >  include/linux/mfd/ti_am335x_tscadc.h | 1 +
> >  2 files changed, 6 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c
> > index d877e777cce6..94ef8992f46b 100644
> > --- a/drivers/mfd/ti_am335x_tscadc.c
> > +++ b/drivers/mfd/ti_am335x_tscadc.c
> > @@ -86,8 +86,12 @@ static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tsadc)
> >  		spin_lock_irq(&tsadc->reg_lock);
> >  		finish_wait(&tsadc->reg_se_wait, &wait);
> >  
> > +		/*
> > +		 * Sequencer should either be idle or
> > +		 * busy applying the charge step.
> > +		 */
> >  		reg = tscadc_readl(tsadc, REG_ADCFSM);
> > -		WARN_ON(reg & SEQ_STATUS);
> > +		WARN_ON(reg & SEQ_STATUS & (!CHARGE_STEP));
> 
> This is almost certainly not correct.
> 
> Please take another look at the logic.
> 
> I'm _assuming_ you mean (reg & SEQ_STATUS && !CHARGE_STEP).

So I just saw that CHARGE_STEP is actually the new macro below.

So you're currently ANDing these together.

xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx  reg
00000000 00000000 00000000 00100000  #define SEQ_STATUS   BIT(5)
00000000 00000000 00000000 00010001  #define CHARGE_STEP  0x11

... which will always equate to 0.

> >  		tsadc->adc_waiting = false;
> >  	}
> >  	tsadc->adc_in_use = true;
> > @@ -96,7 +100,6 @@ static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tsadc)
> >  void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val)
> >  {
> >  	spin_lock_irq(&tsadc->reg_lock);
> > -	tsadc->reg_se_cache |= val;

Didn't you add this line a little over 1 month ago?

Why the change of heart?

> >  	am335x_tscadc_need_adc(tsadc);
> >  
> >  	tscadc_writel(tsadc, REG_SE, val);
> > diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
> > index c99be5dc0f5c..fcce182e4a35 100644
> > --- a/include/linux/mfd/ti_am335x_tscadc.h
> > +++ b/include/linux/mfd/ti_am335x_tscadc.h
> > @@ -128,6 +128,7 @@
> >  
> >  /* Sequencer Status */
> >  #define SEQ_STATUS BIT(5)
> > +#define CHARGE_STEP		0x11
> >  
> >  #define ADC_CLK			3000000
> >  #define TOTAL_STEPS		16
> 

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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