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Date:	Mon, 10 Nov 2014 15:58:52 +0100
From:	Wolfram Sang <wsa@...-dreams.de>
To:	Addy Ke <addy.ke@...k-chips.com>
Cc:	max.schwarz@...ine.de, heiko@...ech.de, olof@...om.net,
	dianders@...omium.org, linux-i2c@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-rockchip@...ts.infradead.org, cf@...k-chips.com,
	xjq@...k-chips.com, huangtao@...k-chips.com, zyw@...k-chips.com,
	yzq@...k-chips.com, hj@...k-chips.com, kever.yang@...k-chips.com,
	hl@...k-chips.com, caesar.wang@...k-chips.com,
	zhengsq@...k-chips.com
Subject: Re: [PATCH v6] i2c: rk3x: adjust the LOW divison based on
 characteristics of SCL

On Tue, Oct 14, 2014 at 02:09:21PM +0800, Addy Ke wrote:
> As show in I2C specification:
> - Standard-mode: the minimum HIGH period of the scl clock is 4.0us
>                  the minimum LOW period of the scl clock is 4.7us
> - Fast-mode: the minimum HIGH period of the scl clock is 0.6us
>              the minimum LOW period of the scl clock is 1.3us
> 
> I have measured i2c SCL waveforms in fast-mode by oscilloscope
> on rk3288-pinky board. the LOW period of the scl clock is 1.3us.
> It is so critical that we must adjust LOW division to increase
> the LOW period of the scl clock.
> 
> Thanks Doug for the suggestion about division formulas.
> 
> Tested-by: Heiko Stuebner <heiko@...ech.de>
> Reviewed-by: Doug Anderson <dianders@...omium.org>
> Tested-by: Doug Anderson <dianders@...omium.org>
> Signed-off-by: Addy Ke <addy.ke@...k-chips.com>

Applied to for-next, thanks!


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