linux-kernel - Re: [PATCH] sparc64: Resolve conflict between sparc v9 and M7 on usage of bit 9 of TTE

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Message-Id: <20141112.133210.2150102649123612493.davem@davemloft.net>
Date:	Wed, 12 Nov 2014 13:32:10 -0500 (EST)
From:	David Miller <davem@...emloft.net>
To:	khalid.aziz@...cle.com
Cc:	bob.picco@...cle.com, sam@...nborg.org, mgorman@...e.de,
	riel@...hat.com, tkhai@...dex.ru, allen.pais@...cle.com,
	sfr@...b.auug.org.au, kirill.shutemov@...ux.intel.com,
	akpm@...ux-foundation.org, sparclinux@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] sparc64: Resolve conflict between sparc v9 and M7 on
 usage of bit 9 of TTE

From: Khalid Aziz <khalid.aziz@...cle.com>
Date: Wed, 12 Nov 2014 09:45:41 -0700

> sparc64: Resolve conflict between sparc v9 and M7 on usage of bit 9 of TTE
> 
> Bit 9 of TTE is CV (Cacheable in V-cache) on sparc v9 processor while
> the same bit 9 is MCDE (Memory Corruption Detection Enable) on M7
> processor. This creates a conflicting usage of the same bit. Kernel
> sets TTE.cv bit on all pages for sun4v architecture which works well
> for sparc v9, but sets memory corruption detection bit on M7 processor
> which is not the intent. This patch adds code to determine if kernel
> is running on M7 processor and takes steps to not enable memory
> corruption detection in TTE erroneously.
> 
> Signed-off-by: Khalid Aziz <khalid.aziz@...cle.com>

The hypervisor specification clearly defines bit 9 as V-Cache
cacheable.

Reusing this bit instead of doing something else was quite unwise if
you ask me.

I also really want a programmers manual for the M7 chip at this point
before I'm willing to apply any patches of this nature.

It's nearly impossible for me to sufficiently review all of the recent
binutils (for new instructions) and now kernel (redefined TTE bits)
changes without access to the programmer's manual.

Thanks.
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