lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Thu, 13 Nov 2014 01:21:16 +0000
From:	"Zhang, Yang Z" <>
To:	"Wu, Feng" <>,
	Paolo Bonzini <>,
	"Alex Williamson" <>
CC:	"" <>,
	"" <>,
	"" <>,
	"" <>,
	"" <>,
	"" <>, "" <>,
	"" <>,
	"" <>,
	"" <>
Subject: RE: [PATCH 05/13] KVM: Update IRTE according to guest interrupt
 configuration changes

Wu, Feng wrote on 2014-11-13:
> wrote on 2014-11-12:
>> Subject: Re: [PATCH 05/13] KVM: Update IRTE according to guest 
>> interrupt configuration changes
>> On 12/11/2014 10:19, Wu, Feng wrote:
>>>> You can certainly backport these patches to distros that do not 
>>>> have VFIO.  But upstream we should work on VFIO first.  VFIO has 
>>>> feature parity with legacy device assignment, and adding a new 
>>>> feature that is not in VFIO would be a bad idea.
>>>> By the way, do you have benchmark results for it?  We have not been 
>>>> able to see any performance improvement for APICv on e.g. netperf.
>>> Do you mean benchmark results for APICv itself or VT-d Posted-Interrtups?
>> Especially for VT-d posted interrupts---but it'd be great to know 
>> which workloads see the biggest speedup from APICv.
> We have some draft performance data internally, please see the 
> attached. For VT-d PI, I think we can get the biggest performance gain 
> if the VCPU is running in non-root mode for most of the time (not in 
> HLT state), since external interrupt from assigned devices will be delivered by guest directly in this case.
> That means we can run some cpu intensive workload in the guests.

Have you check that the CPU side posted interrupt is taking effect in w/o VT-D PI case? Per my understanding, the performance gap should be so large if you use CPU side posted interrupt. This data more like the VT-d PI vs non PI(both VT-d and CPU).

> Thanks,
> Feng
>> Paolo
>> --
>> To unsubscribe from this list: send the line "unsubscribe kvm" in the 
>> body of a message to More majordomo info at 

Best regards,

Powered by blists - more mailing lists