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Message-Id: <1415935631-16826-1-git-send-email-andy.yan@rock-chips.com>
Date: Fri, 14 Nov 2014 11:27:11 +0800
From: Andy Yan <andy.yan@...k-chips.com>
To: airlied@...ux.ie, heiko@...ech.de, fabio.estevam@...escale.com,
rmk+kernel@....linux.org.uk
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Grant Likely <grant.likely@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Shawn Guo <shawn.guo@...aro.org>,
Josh Boyer <jwboyer@...hat.com>,
Sean Paul <seanpaul@...omium.org>,
Inki Dae <inki.dae@...sung.com>,
Dave Airlie <airlied@...hat.com>,
Arnd Bergmann <arnd@...db.de>,
Lucas Stach <l.stach@...gutronix.de>,
Zubair.Kakakhel@...tec.com, djkurtz@...gle.com, ykk@...k-chips.com,
linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
devel@...verdev.osuosl.org, devicetree@...r.kernel.org,
linux-rockchip@...ts.infradead.org, jay.xu@...k-chips.com,
Pawel Moll <pawel.moll@....com>, mark.yao@...k-chips.com,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Andy Yan <andy.yan@...k-chips.com>
Subject: [PATCH v10 05/11] drm: bridge/dw_hdmi:split some phy configuration to platform driver
hdmi phy clock symbol and transmission termination value
can adjust platform specific to get the best SI
also add mode_valid interface for some platform may not support
all the display mode
Signed-off-by: Andy Yan <andy.yan@...k-chips.com>
---
Changes in v10:
- split generic dw_hdmi.c improvements from patch#11 (add rk3288 support)
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/bridge/dw_hdmi.c | 29 +++++++++++++++++++++++++++--
drivers/staging/imx-drm/dw_hdmi-imx.c | 10 +++++++++-
include/drm/bridge/dw_hdmi.h | 7 +++++++
3 files changed, 43 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c
index e9f0dfe..05e7156 100644
--- a/drivers/gpu/drm/bridge/dw_hdmi.c
+++ b/drivers/gpu/drm/bridge/dw_hdmi.c
@@ -718,6 +718,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
u8 val, msec;
const struct mpll_config *mpll_cfg = hdmi->plat_data->mpll_cfg;
const struct curr_ctrl *curr_ctr = hdmi->plat_data->cur_ctr;
+ const struct sym_term *sym_term = hdmi->plat_data->sym_term;
if (prep)
return -EINVAL;
@@ -787,10 +788,17 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
+
+ for (i = 0; sym_term[i].mpixelclock != (~0UL); i++)
+ if (hdmi->hdmi_data.video_mode.mpixelclock <=
+ sym_term[i].mpixelclock)
+ break;
+
/* RESISTANCE TERM 133Ohm Cfg */
- hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */
+ hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19); /* TXTERM */
/* PREEMP Cgf 0.00 */
- hdmi_phy_i2c_write(hdmi, 0x800d, 0x09); /* CKSYMTXCTRL */
+ hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09); /* CKSYMTXCTRL */
+
/* TX/CK LVL 10 */
hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
/* REMOVE CLK TERM */
@@ -1326,6 +1334,20 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
return 0;
}
+static enum drm_mode_status
+dw_hdmi_connector_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct dw_hdmi *hdmi = container_of(connector,
+ struct dw_hdmi, connector);
+ enum drm_mode_status mode_status = MODE_OK;
+
+ if (hdmi->plat_data->mode_valid)
+ mode_status = hdmi->plat_data->mode_valid(connector, mode);
+
+ return mode_status;
+}
+
static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
*connector)
{
@@ -1416,6 +1438,7 @@ static struct drm_connector_funcs dw_hdmi_connector_funcs = {
static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
.get_modes = dw_hdmi_connector_get_modes,
+ .mode_valid = dw_hdmi_connector_mode_valid,
.best_encoder = dw_hdmi_connector_best_encoder,
};
@@ -1487,6 +1510,8 @@ static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
+ drm_connector_register(&hdmi->connector);
+
return 0;
}
diff --git a/drivers/staging/imx-drm/dw_hdmi-imx.c b/drivers/staging/imx-drm/dw_hdmi-imx.c
index 4b48ea6..d693051 100644
--- a/drivers/staging/imx-drm/dw_hdmi-imx.c
+++ b/drivers/staging/imx-drm/dw_hdmi-imx.c
@@ -69,7 +69,13 @@ static const struct curr_ctrl imx_cur_ctr[] = {
}
};
-static int dw_hdmi_parse_dt(struct imx_hdmi *hdmi)
+static const struct sym_term imx_sym_term[] = {
+ /*pixelclk symbol term*/
+ { 148500000, 0x800d, 0x0005 },
+ { ~0UL, 0x0000, 0x0000 }
+};
+
+static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
{
struct device_node *np = hdmi->dev->of_node;
@@ -156,6 +162,7 @@ static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
.encoder_prepare = dw_hdmi_imx_encoder_prepare,
.mpll_cfg = imx_mpll_cfg,
.cur_ctr = imx_cur_ctr,
+ .sym_term = imx_sym_term,
.dev_type = IMX6Q_HDMI,
};
@@ -166,6 +173,7 @@ static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
.encoder_prepare = dw_hdmi_imx_encoder_prepare,
.mpll_cfg = imx_mpll_cfg,
.cur_ctr = imx_cur_ctr,
+ .sym_term = imx_sym_term,
.dev_type = IMX6DL_HDMI,
};
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 6683b63..1688ec9 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -37,6 +37,12 @@ struct curr_ctrl {
u16 curr[RES_MAX];
};
+struct sym_term {
+ unsigned long mpixelclock;
+ u16 sym_ctr; /*clock symbol and transmitter control*/
+ u16 term; /*transmission termination value*/
+};
+
struct dw_hdmi_plat_data {
void * (*setup)(struct platform_device *pdev);
void (*exit)(void *priv);
@@ -47,6 +53,7 @@ struct dw_hdmi_plat_data {
struct drm_display_mode *mode);
const struct mpll_config *mpll_cfg;
const struct curr_ctrl *cur_ctr;
+ const struct sym_term *sym_term;
enum dw_hdmi_devtype dev_type;
};
--
1.9.1
--
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