linux-kernel - Re: [PATCH] clk: rockchip: fix clock select order for usbphy480m

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Message-ID: <8965478.SpyRElfG0W@diego>
Date:	Sun, 16 Nov 2014 00:41:27 +0100
From:	Heiko Stübner <heiko@...ech.de>
To:	Kever Yang <kever.yang@...k-chips.com>
Cc:	Mike Turquette <mturquette@...aro.org>, dianders@...omium.org,
	sonnyrao@...omium.org, addy.ke@...k-chips.com, cf@...k-chips.com,
	dkl@...k-chips.com, huangtao@...k-chips.com,
	linux-rockchip@...ts.infradead.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: rockchip: fix clock select order for usbphy480m_src

Am Donnerstag, 13. November 2014, 16:11:49 schrieb Kever Yang:
> According to rk3288 trm, the mux selector locate at bit[12:11]
> of CRU_CLKSEL13_CON shows:
> 2'b00: select HOST0 USB pll clock (clk_otgphy1)
> 2'b01: select HOST1 USB pll clock (clk_otgphy2)
> 2'b10: select OTG USB pll clock   (clk_otgphy0)
> 
> The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
> - clk_otgphy0 -> USB PHY OTG
> - clk_otgphy1 -> USB PHY host0
> - clk_otgphy2 -> USB PHY host1
> 
> Signed-off-by: Kever Yang <kever.yang@...k-chips.com>

applied this to my clk branch for 3.19


Heiko
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