linux-kernel - Re: [PATCH v2 1/2] clk: rockchip: add bindings for the mmc clock phases

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Message-ID: <CAHNYxRwGWqbznVybmE+tpyghEoQwVFK_V2ubFRKXasvsPS+R7Q@mail.gmail.com>
Date:	Mon, 17 Nov 2014 11:50:51 -0800
From:	Alexandru Stan <amstan@...omium.org>
To:	Mike Turquette <mturquette@...aro.org>
Cc:	Heiko Stuebner <heiko@...ech.de>,
	Doug Anderson <dianders@...omium.org>,
	addy ke <addy.ke@...k-chips.com>,
	Sonny Rao <sonnyrao@...omium.org>,
	Kever Yang <kever.yang@...k-chips.com>,
	linux-rockchip@...ts.infradead.org,
	linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
	robh+dt@...nel.org, pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	mark.yao@...k-chips.com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/2] clk: rockchip: add bindings for the mmc clock phases

Sorry for my previous mail, I sent it as HTML and also top posted.
Here it goes again:

On Mon, Nov 17, 2014 at 11:39 AM, Mike Turquette <mturquette@...aro.org> wrote:
> It looks like you are adding new clocks to handle the phase requirement.
> Is that the right thing to do? Don't these clks already exist (e.g.
> SCLK_SDMMC)?
I actually need to control 2 phases, one of them is used when
outputting data, the other when sampling. Sunxi does something
similar: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/273273.html

Another reason it wouldn't work is because the upstream clock(eg
SCLK_SDMMC) is twice as fast as the real clock(see RK3288_CLKGEN_DIV
in drivers/mmc/host/dw_mmc-rockchip.c), since that clock goes to a /2
divider to be able to do the 90 degree clock phases.

Alexandru Stan
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