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Message-ID: <20141118172644.26303.37688.stgit@ahduyck-server>
Date: Tue, 18 Nov 2014 09:28:47 -0800
From: Alexander Duyck <alexander.h.duyck@...hat.com>
To: linux-arch@...r.kernel.org, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: mathieu.desnoyers@...ymtl.ca, peterz@...radead.org,
benh@...nel.crashing.org, heiko.carstens@...ibm.com,
mingo@...nel.org, mikey@...ling.org, linux@....linux.org.uk,
donald.c.skidmore@...el.com, matthew.vick@...el.com,
geert@...ux-m68k.org, jeffrey.t.kirsher@...el.com,
romieu@...zoreil.com, paulmck@...ux.vnet.ibm.com,
nic_swsd@...ltek.com, will.deacon@....com, michael@...erman.id.au,
tony.luck@...el.com, torvalds@...ux-foundation.org,
oleg@...hat.com, schwidefsky@...ibm.com, fweisbec@...il.com,
davem@...emloft.net
Subject: [PATCH v4 0/4] Add lightweight memory barriers for coherent memory
access
These patches introduce two new primitives for synchronizing cache coherent
memory writes and reads. These two new primitives are:
coherent_rmb()
coherent_wmb()
The first patch cleans up some unnecessary overhead related to the
definition of read_barrier_depends, smp_read_barrier_depends, and comments
related to the barrier.
The second patch adds the primitives for the applicable architectures and
asm-generic.
The third patch adds the barriers to r8169 which turns out to be a good
example of where the new barriers might be useful as they have full
rmb()/wmb() barriers ordering accesses to the descriptors and the DescOwn
bit.
The fourth patch adds support for coherent_rmb() to the Intel fm10k, igb,
and ixgbe drivers. Testing with the ixgbe driver has shown a processing
time reduction of at least 7ns per 64B frame on a Core i7-4930K.
This patch series is essentially the v4 for:
v3: Add lightweight memory barriers fast_rmb() and fast_wmb()
v2: Introduce load_acquire() and store_release()
v1: Introduce read_acquire()
The key changes in this patch series versus the earlier patches are:
v4:
- Updated ARM barrier domains to outer shareable
- Renamed barriers coherent_rmb and coherent_wmb
- Added smp_lwsync for use in smp_load_acquire/smp_store_release
v3:
- Moved away from acquire()/store() and instead focused on barriers
- Added cleanup of read_barrier_depends
- Added change in r8169 to fix cur_tx/DescOwn ordering
- Simplified changes to just replacing/moving barriers in r8169
- Added update to documentation with code example
v2:
- Renamed read_acquire() to be consistent with smp_load_acquire()
- Changed barrier used to be consistent with smp_load_acquire()
- Updated PowerPC code to use __lwsync based on IBM article
- Added store_release() as this is a viable use case for drivers
- Added r8169 patch which is able to fully use primitives
- Added fm10k/igb/ixgbe patch which is able to test performance
---
Alexander Duyck (4):
arch: Cleanup read_barrier_depends() and comments
arch: Add lightweight memory barriers coherent_rmb() and coherent_wmb()
r8169: Use coherent_rmb() and coherent_wmb() for DescOwn checks
fm10k/igb/ixgbe: Use coherent_rmb on Rx descriptor reads
Documentation/memory-barriers.txt | 41 +++++++++++++++
arch/alpha/include/asm/barrier.h | 51 ++++++++++++++++++
arch/arm/include/asm/barrier.h | 4 +
arch/arm64/include/asm/barrier.h | 3 +
arch/blackfin/include/asm/barrier.h | 51 ++++++++++++++++++
arch/ia64/include/asm/barrier.h | 25 ++++-----
arch/metag/include/asm/barrier.h | 19 ++++---
arch/mips/include/asm/barrier.h | 61 ++--------------------
arch/powerpc/include/asm/barrier.h | 23 +++++---
arch/s390/include/asm/barrier.h | 7 ++-
arch/sparc/include/asm/barrier_64.h | 7 ++-
arch/x86/include/asm/barrier.h | 70 ++++---------------------
arch/x86/um/asm/barrier.h | 20 ++++---
drivers/net/ethernet/intel/fm10k/fm10k_main.c | 6 +-
drivers/net/ethernet/intel/igb/igb_main.c | 6 +-
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 9 +--
drivers/net/ethernet/realtek/r8169.c | 29 ++++++++--
include/asm-generic/barrier.h | 8 +++
18 files changed, 259 insertions(+), 181 deletions(-)
--
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