linux-kernel - Re: [PATCH 15/15] metag: tz1090: add TZ1090 clocks to device tree

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Date:	Fri, 21 Nov 2014 10:06:47 +0000
From:	James Hogan <james.hogan@...tec.com>
To:	Heiko Stübner <heiko@...ech.de>
CC:	Mike Turquette <mturquette@...aro.org>,
	<linux-metag@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<devicetree@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	"Kumar Gala" <galak@...eaurora.org>
Subject: Re: [PATCH 15/15] metag: tz1090: add TZ1090 clocks to device tree

On Thu, Nov 20, 2014 at 01:56:24PM +0100, Heiko Stübner wrote:
> Hi James,
> 
> interestingly I only got the cover-letter, so had to find the other patches 
> through my list-archive :-) .

Hmm, sorry about that. I copy cover letter Cc list from the Ccs of the
patches, so not sure what happened there.

> 
> 
> Am Mittwoch, 19. November 2014, 23:15:43 schrieb James Hogan:
> > Enable the common clock framework for the TZ1090 SoC, add a tz1090_clk
> > device tree file describing the clocks, and connect the Meta core clock
> > so that the rate of the Meta timer can be determined.
> > 
> > Most of the clock tree is described apart from some AFE clocks which
> > aren't usually of much interest to Linux. These are represented with
> > placeholder clocks.
> > 
> > Signed-off-by: James Hogan <james.hogan@...tec.com>
> > Cc: Mike Turquette <mturquette@...aro.org>
> > Cc: Rob Herring <robh+dt@...nel.org>
> > Cc: Pawel Moll <pawel.moll@....com>
> > Cc: Mark Rutland <mark.rutland@....com>
> > Cc: Ian Campbell <ijc+devicetree@...lion.org.uk>
> > Cc: Kumar Gala <galak@...eaurora.org>
> > Cc: linux-metag@...r.kernel.org
> > Cc: devicetree@...r.kernel.org
> > ---
> 
> 
> I don't know enough about your clock structure, but it looks quite a bit like 
> Mike's mail from May [0] may apply here too.
> 
> The register layout also suggests that it is indeed one clock ip-block:
> 
> 0x02005908 0x4	CR_TOP_CLKSWITCH 
> 0x0200590c 0x4	CR_TOP_CLKENAB
> 0x02005950 0x4	CR_TOP_SYSPLL_CTL0
> 0x02005954 0x4	CR_TOP_SYSPLL_CTL1
> 0x02005988 0x4	CR_TOP_CLKSWITCH2
> 0x0200598c 0x4	CR_TOP_CLKENAB2
> ...
> 
> 
> [0] https://lkml.org/lkml/2014/5/14/715

Thanks, that does make sense. It's probably more like 4 memory regions
("top" level, "perip" peripheral registers, "hep" high end peripheral
registers, and "pdc" powerdown controller registers), but it could
certainly still have a single binding with multiple memory regions to
simplify the clock specifiers.

I'll take a look at doing it that way.

Cheers
James

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