linux-kernel - [PATCH 10/11] arm64: dts: Enable USB 3.0 controller on exynos7

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Date:	Fri, 21 Nov 2014 19:05:53 +0530
From:	Vivek Gautam <gautam.vivek@...sung.com>
To:	linux-kernel@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
	linux-usb@...r.kernel.org, devicetree@...r.kernel.org,
	balbi@...com, kishon@...com
Cc:	linux-omap@...r.kernel.org, gregkh@...uxfoundation.org,
	tomasz.figa@...il.com, s.nawrocki@...sung.com, robh+dt@...nel.org,
	stern@...land.harvard.edu, kgene.kim@...sung.com,
	Vivek Gautam <gautam.vivek@...sung.com>
Subject: [PATCH 10/11] arm64: dts: Enable USB 3.0 controller on exynos7

Adding USB 3.0 DRD controller device node, with its clock
and phy information to enable using the same on Exynos7.

Signed-off-by: Vivek Gautam <gautam.vivek@...sung.com>
---
 arch/arm64/boot/dts/exynos/exynos7.dtsi |   35 +++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 90048b2..e633b02 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -531,6 +531,41 @@
 			clocks = <&clock_peric0 PCLK_PWM>;
 			clock-names = "timers";
 		};
+
+		usbdrd3: usb@...00000 {
+			compatible = "samsung,exynos7-dwusb3";
+			clocks = <&clock_fsys0 ACLK_USBDRD300>,
+				 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
+				 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
+			clock-names = "usbdrd30", "usbdrd30_susp_clk",
+				      "usbdrd30_axius_clk";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			dwc3 {
+				compatible = "snps,dwc3";
+				reg = <0x15400000 0x10000>;
+				interrupts = <0 223 0>;
+				phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
+		usbdrd_phy: phy@...00000 {
+			compatible = "samsung,exynos7-usbdrd-phy";
+			reg = <0x15500000 0x100>;
+			clocks =
+			  <&clock_fsys0 ACLK_USBDRD300>,
+			  <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
+			  <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
+			  <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
+			  <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
+			clock-names = "phy", "ref", "phy_pipe", "phy_utmi",
+				      "itp";
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			#phy-cells = <1>;
+		};
 	};
 };
 
-- 
1.7.10.4

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