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Message-ID: <546E9F8C.4050307@huawei.com>
Date:	Fri, 21 Nov 2014 10:12:28 +0800
From:	Yijing Wang <wangyijing@...wei.com>
To:	Jiang Liu <jiang.liu@...ux.intel.com>,
	Thomas Gleixner <tglx@...utronix.de>
CC:	Marc Zyngier <marc.zyngier@....com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-pci@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Will Deacon <will.deacon@....com>,
	Catalin Marinas <catalin.marinas@....com>,
	"H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...nel.org>,
	Arjan van de Ven <arjan@...radead.org>,
	David Woodhouse <dwmw2@...radead.org>
Subject: Re: Removal of bus->msi assignment breaks MSI with stacked domains

On 2014/11/21 10:03, Jiang Liu wrote:
> On 2014/11/21 9:46, Thomas Gleixner wrote:
>> On Fri, 21 Nov 2014, Yijing Wang wrote:
>>> On 2014/11/21 0:31, Marc Zyngier wrote:
>>>> Bjorn, Yijing,
>>>>
>>>> I've just realized that patch c167caf8d174 (PCI/MSI: Remove useless
>>>> bus->msi assignment) completely breaks MSI on arm64 when using the new
>>>> MSI stacked domain:
>>>
>>> Sorry, this is my first part to refactor MSI related code, now how
>>> to get pci msi_controller depends arch
>>> functions(pcibios_msi_controller() or arch_setup_msi_irq()), we are
>>> working on generic pci_host_bridge, after that, we could eventually
>>> eliminate MSI arch functions and find pci dev 's msi controller by
>>> pci_host_bridge->get_msi_controller().
>>
>> The main question is why you think that pci_host_bridge is the proper
>> place to store that information.
>>
>> On x86 we have DMAR units associated to a single device. Each DMAR
>> unit is a seperate MSI irq domain. 
>>
>> Can you guarantee that the pci_host_bridge is the right point to
>> provide the association of the device to the irq domain?
>>
>> So the real question is:
>>
>>    What is the association level requirement to properly identify the
>>    irqdomain for a specific device on any given architecture with and
>>    without IOMMU, interrupt redirection etc.
>>
>> To be honest: I don't know.
>>
>> My gut feeling tells me that it's at the device level, but I really
>> leave that decision to the experts in that field.
> Hi Thomas and Yijing,
> 	Since we are allocating interrupts for a PCI device, it's
> natural to get irqdomain from the PCI device itself. If we try to
> get irqdomain from a PCI bus or host bridge like
> pci_get_msi_irqdomain(bus or hostbridge), it may fail for x86
> because x86 may build per-device irqdomain theoretically.
> So the preferred interface prototype is:
> 	pci_get_msi_irqdomain(pci_dev) or
> 	pcibios_msi_controller(pci_dev)
> It's flexible enough. For architectures on which irqdomain is
> associated with PCI bus or host bridge, you could get the bus
> or host bridge from pci_dev. And it won't cause extra computation
> because you always need to get bus or host bridge from the pci_dev.

Hi Gerry, I mean we could find msi_controller by calling
pci_host_bridge->pci_get_msi_irqdomain/msi_controller(struct pci_dev *pdev)
to avoid arch weak function like pcibios_get_msi_controller(struct pci_dev *pdev). :)


> Regards!
> Gerry
>>
>> Thanks,
>>
>> 	tglx
>>
> 
> .
> 


-- 
Thanks!
Yijing

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