linux-kernel - Re: [PATCH] x86: Intel Cache Allocation Technology support

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Message-ID: <546FA0C4.1000402@intel.com>
Date:	Fri, 21 Nov 2014 12:29:56 -0800
From:	Dave Hansen <dave.hansen@...el.com>
To:	Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
	linux-kernel@...r.kernel.org
CC:	vikas.shivappa@...el.com, hpa@...or.com, tglx@...utronix.de,
	mingo@...nel.org, tj@...nel.org, matt.flemming@...el.com,
	will.auld@...el.com, peterz@...radead.org
Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support

On 11/19/2014 05:05 PM, Vikas Shivappa wrote:
> +	/*
> +	 * Hard code the checks and values for HSW SKUs.
> +	 * Unfortunately! have to check against only these brand name strings.
> +	 */
> +
> +	for (i = 0; i < 5; i++)
> +		if (!strcmp(hsw_brandstrs[i], c->x86_model_id)) {
> +			c->x86_cqe_closs = 4;
> +			c->x86_cqe_cbmlength = 20;
> +			return true;
> +		}

Please use ARRAY_SIZE() here.  Otherwise, I guarantee the next string
you add to hsw_brandstrs[] gets silently ignored.

Are there really only 5 CPUs?  This:

> http://ark.intel.com/products/family/78583/Intel-Xeon-Processor-E5-v3-Family#@Server

lists 32 skus.
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