linux-kernel - Re: [PATCH] x86: Intel Cache Allocation Technology support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <alpine.DEB.2.10.1411211313200.30781@vshiva-Udesk>
Date:	Fri, 21 Nov 2014 13:14:53 -0800 (PST)
From:	Vikas Shivappa <vikas.shivappa@...el.com>
To:	Borislav Petkov <bp@...en8.de>
cc:	Vikas Shivappa <vikas.shivappa@...el.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...nel.org,
	tj@...nel.org, matt.flemming@...el.com, will.auld@...el.com,
	peterz@...radead.org
Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support



On Fri, 21 Nov 2014, Borislav Petkov wrote:

> On Fri, Nov 21, 2014 at 12:00:27PM -0800, Vikas Shivappa wrote:
>>>> +char hsw_brandstrs[5][64] = {
>>>> +			"Intel(R) Xeon(R)  CPU E5-2658 v3  @  2.20GHz",
>>>> +			"Intel(R) Xeon(R)  CPU E5-2648L v3  @  1.80GHz",
>>>> +			"Intel(R) Xeon(R)  CPU E5-2628L v3  @  2.00GHz",
>>>> +			"Intel(R) Xeon(R)  CPU E5-2618L v3  @  2.30GHz",
>>>> +			"Intel(R) Xeon(R)  CPU E5-2608L v3  @  2.00GHz"
>>>> +};
>>>> +
>>>> +#define cacheqe_for_each_child(child_cq, pos_css, parent_cq)		\
>>>> +	css_for_each_child((pos_css),	\
>>>> +	&(parent_cq)->css)
>>>> +
>>>> +#if CONFIG_CACHEQE_DEBUG
>>>
>>> We really do NOT need another config option for this. See above.
>>>
>>>> +/*DUMP the closid-cbm map.*/
>>>
>>> Wow that comment is really informative.
>>>
>>>> +static inline bool cqe_enabled(struct cpuinfo_x86 *c)
>>>> +{
>>>> +
>>>> +	int i;
>>>> +
>>>> +	if (cpu_has(c, X86_FEATURE_CQE_L3))
>>>> +		return true;
>>>> +
>>>> +	/*
>>>> +	 * Hard code the checks and values for HSW SKUs.
>>>> +	 * Unfortunately! have to check against only these brand name strings.
>>>> +	 */
>>>
>>> You must be kidding.
>>
>> No. Will have a microcode version check as well in next patch after thats
>> confirmed from h/w team
>
> Checking random brand strings? Please don't tell me those are not really
> immutable either...
>
> And what happens with newer models appearing? Add more brand strings?
> Lovely stuff, that.
>
> Well, since you're talking to the h/w team: can they give you some
> immutable bit somewhere which you can check instead of looking at brand
> strings? This'll be a sane solution, actually.
>

Yes , I did check for something like model stepping , not received anything yet. 
will update in my next version.

Thanks,
Vikas

> -- 
> Regards/Gruss,
>    Boris.
>
> Sent from a fat crate under my desk. Formatting is fine.
> --
>
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/