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Message-ID: <CAJe_ZheyfmX-bcuqGQk4vKA1DFJYgr69w2B_9rxf3POKHWqYyA@mail.gmail.com>
Date:	Mon, 24 Nov 2014 14:48:31 +0530
From:	Jassi Brar <jaswinder.singh@...aro.org>
To:	Andrew Bresticker <abrestic@...omium.org>
Cc:	Stephen Warren <swarren@...dotorg.org>,
	Thierry Reding <thierry.reding@...il.com>,
	Alexandre Courbot <gnurou@...il.com>,
	"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
	Mark Rutland <mark.rutland@....com>,
	Devicetree List <devicetree@...r.kernel.org>,
	Linux USB list <linux-usb@...r.kernel.org>,
	Russell King <linux@....linux.org.uk>,
	Mathias Nyman <mathias.nyman@...el.com>,
	Pawel Moll <pawel.moll@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Jassi Brar <jassisinghbrar@...il.com>,
	lkml <linux-kernel@...r.kernel.org>,
	Kishon Vijay Abraham I <kishon@...com>,
	Olof Johansson <olof@...om.net>,
	Rob Herring <robh+dt@...nel.org>,
	Alan Stern <stern@...land.harvard.edu>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Kumar Gala <galak@...eaurora.org>,
	Grant Likely <grant.likely@...aro.org>,
	Arnd Bergmann <arnd@...db.de>
Subject: Re: [PATCH V5 07/12] pinctrl: tegra-xusb: Add USB PHY support

On 18 November 2014 at 04:11, Andrew Bresticker <abrestic@...omium.org> wrote:
> In addition to the PCIe and SATA PHYs, the XUSB pad controller also
> supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs.  Each USB3 PHY uses a single
> PCIe or SATA lane and is mapped to one of the three UTMI ports.
>
> The xHCI controller will also send messages intended for the PHY driver,
> so request and listen for messages on the mailbox's PHY channel.
>
> Signed-off-by: Andrew Bresticker <abrestic@...omium.org>
> Acked-by: Linus Walleij <linus.walleij@...aro.org>
> Reviewed-by: Stephen Warren <swarren@...dia.com>

Mailbox bits look good to me.

-Jassi
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