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Message-ID: <CAMAWPa8whctBR6fBFaSzPvm3qn+QK06CimRrxFxxH=0kNkF4UA@mail.gmail.com>
Date: Mon, 24 Nov 2014 11:08:48 -0800
From: Kevin Hilman <khilman@...nel.org>
To: Alexander Kochetkov <al.kochet@...il.com>,
Felipe Balbi <balbi@...com>, Tony Lindgren <tony@...mide.com>
Cc: linux-omap <linux-omap@...r.kernel.org>, linux-i2c@...r.kernel.org,
lkml <linux-kernel@...r.kernel.org>,
Wolfram Sang <wsa@...-dreams.de>
Subject: Re: [PATCH v3 2/4] i2c: omap: implement workaround for handling
invalid BB-bit values
On Sat, Nov 22, 2014 at 11:47 AM, Alexander Kochetkov
<al.kochet@...il.com> wrote:
> In a multimaster environment, after IP software reset, BB-bit value doesn't
> correspond to the current bus state. It may happen what BB-bit will be 0,
> while the bus is busy due to another I2C master activity.
>
> Any transfer started when BB=0 and bus is busy wouldn't be completed by IP
> and results in controller timeout. More over, in some cases IP could
> interrupt another master's transfer and corrupt data on wire.
>
> The commit implement method allowing to prevent IP from entering into
> "controller timeout" state and from "data corruption" state.
>
> The one drawback is the need to wait for 10ms before the first transfer.
>
> Tested on Beagleboard XM C.
> Tested on BBB and AM437x Starter Kit by Felipe Balbi.
>
> Signed-off-by: Alexander Kochetkov <al.kochet@...il.com>
> Tested-by: Felipe Balbi <balbi@...com>
> Reviewed-by: Felipe Balbi <balbi@...com>
This patch recently hit linux-next (as commit 903c3859f77f) and boot
breakage[1] in next-20141124 on OMAP3530 Beagle and Overo/Tobi boards
was bisected down to this commit.
Kevin
[1] http://status.armcloud.us/boot/?next-20141124&omap
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